Design Methodology Lead - Physical Design Flows

Analog Devices; Wilmington (DE); On-site; USD 117,000 - 161,000; Full time

Benefits offered by this job

Discretionary bonus

Medical coverage

401k plan

Paid vacation & holidays

Job summary

Analog Devices is seeking a Design Engineer to lead physical design methodology improvements across complex chip and SoC programs. The role emphasizes flow standardization, reuse, and measurable improvements, working with CAD, STA, DFT, RTL, and design teams.

You will drive automation, define guardrails, and analyze QoR to push for durable, scalable flow solutions. Strong collaboration and troubleshooting across teams are essential for success.

Qualifications

• Bachelor’s degree in electrical engineering, Computer Engineering, or a related field
• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field
• 8+ years of related experience (Bachelor) or 5+ years (Master/PhD)

Responsibilities

• Drive improvements to physical design methodology and flow standardization
• Own development, refinement, and maintenance of flows, scripts, and automation
• Define guardrails and best practices for reuse across teams and programs
• Analyze QoR, timing, power, area, and congestion to identify gaps
• Collaborate with cross-functional teams to enable adoption of improvements
• Investigate root causes of convergence issues and implement corrective actions
• Provide guidance on methodology usage and flow adoption
• Support implementation validation and troubleshooting of critical flow issues

Skills

Methodology development

Flow development

Digital physical design fundamentals

EDA tool experience

Scripting and automation

Cross-functional communication

Technical judgment

Education

Bachelor’s degree in electrical/Computer engineering or related field

Master’s or PhD in Electrical/Computer engineering or related field

Tools

Synopsys tools

Cadence tools

Job description

Analog Devices is seeking a Design Engineer to lead physical design methodology improvements across complex chip and SoC programs. The role emphasizes flow standardization, reuse, and measurable improvements, working with CAD, STA, DFT, RTL, and design teams.

You will drive automation, define guardrails, and analyze QoR to push for durable, scalable flow solutions. Strong collaboration and troubleshooting across teams are essential for success.