Design Engineer- (Standard and Custom Cell Characterization) -HBM

micron; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Micron Technology is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure for HBM and related products. You will develop flows that support timing, power, and reliability modeling across multiple process nodes, including Micron internal nodes and external foundries such as TSMC.

You will collaborate with design, verification, and CAD teams to improve model accuracy, automate routines, and ensure silicon correlation and scalable signoffs for

Qualifications

• Bachelor's or Master's in Electrical Engineering or related field.
• Strong fundamentals in CMOS digital/mixed-signal design and PVT variation.
• Experience with standard or custom cell characterization, Liberty modeling, and SPICE.
• Proficiency in Python, Perl, or Tcl for automation.

Responsibilities

• Develop and sustain scalable infrastructure for standard and custom cell characterization.
• Build automated flows for multi-corner, multi-mode characterization across PVT spaces.
• Enable characterization across diverse process technologies including Micron and external foundries like TSMC.
• Support characterization for core dies and advanced HBM architectures.
• Collaborate with design teams to align characterization with performance and power targets.
• Lead debug and validation; improve model accuracy and data quality for signoff.

Skills

CMOS fundamentals

PVT variation

STA flows

Liberty modeling

SPICE-based simulation

Python scripting

Tcl scripting

Perl scripting

Education

Electrical Engineering degree

Tools

SiliconSmart

PrimeLib

Job description

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry.

Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic developments.

This position includes characterizing both standard and custom cells across various process technologies. These encompass Micron internal nodes as well as external foundries, such as TSMC. The position supports multiple HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures.

You will work where circuit build, EDA infrastructure, and silicon validation readiness meet. You will develop robust, scalable, and high-quality characterization flows. These flows directly affect timing closure, power modeling, and product quality for next-generation HBM programs.

Responsibilities:

• Develop and sustain scalable infrastructure for standard cell and custom cell characterization, encompassing timing, power, noise, and signal integrity modeling.
• Build reusable, automated flows that support multi-corner, multi-mode (MCMM) characterization across extensive PVT spaces. Develop robust Liberty model generation, validation, and regression frameworks to ensure high-quality results for downstream design and signoff flows.
• Enable characterization across diverse process technologies, including Micron internal nodes and external foundries such as TSMC. Address technology-specific challenges such as variability, layout-dependent effects, aging, and reliability, and promote consistent approaches that allow seamless portability and standardization across multiple process nodes.
• Support characterization requirements across various HBM product verticals, including core dies and multiple custom base dies. Also support emerging advanced HBM architectures. Collaborate closely with design teams to develop characterization requirements for specialized circuit classes like TSV interfaces, PHY-critical paths, and high-speed datapath elements. Ensure these align with system-level performance and power targets.
• Integrate characterization flows into broader build and verification ecosystems by partnering with design, verification, and CAD teams. Drive improvements in model accuracy, turnaround time, and silicon correlation while establishing standard processes for corner definition, quality metrics, and data consistency across IPs and programs.
• Lead debug, validation, and continuous improvement efforts by root-causing mismatches between SPICE, extracted views, STA, and silicon behavior. Develop metrics, dashboards, and automated checks to ensure completeness, adaptability, and quality of characterization data, enabling reliable signoff and scalable deployment across future HBM programs.

Minimum Qualifications:

• Bachelor's or Master's Degree or equivalent experience in Electrical Engineering or a related field, along with strong fundamentals in CMOS digital and mixed-signal circuit development, device physics, and PVT variation.
• Practical experience with standard or custom cell characterization procedures-including Liberty modeling (CCS/ECSM or equivalent) and SPICE-based simulation-is essential.
• A solid understanding of STA flows and timing libraries, combined with proficiency in scripting languages such as Python, Perl, or Tcl for automation, is required.

Preferred Qualifications:

• Experience in SiliconSmart or PrimeLib is preferred.
• Experience working across multiple semiconductor process technologies is highly desirable.
• Experience in HBM, DRAM, or high-speed interface development is preferred, particularly in environments involving advanced foundry PDKs such as TSMC nodes.
• Familiarity with high-speed PHY development, TSV-aware considerations, and advanced modeling topics such as signal integrity, EMIR effects, aging, and reliability will differentiate candidates.
• Prior exposure to infrastructure or methodology development-beyond just using characterization flows-is strongly valued, as this role requires building scalable solutions rather than implementing predefined flows.
• Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

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