Electrical Design and Analysis Engineer 3

CHIPTON-ROSS Inc.; El Segundo (CA); On-site; USD 83,000 - 131,000; Full time

Job summary

Chipton-Ross is seeking an Electrical Design and Analysis Engineer 3 for a contract opportunity in El Segundo, CA. 100% onsite.

The ideal candidate will have 2+ years of FPGA design experience with strong Xilinx/AMD Vivado expertise and Verilog/SystemVerilog proficiency. You will analyze requirements, create architectures, implement HDL blocks, perform synthesis and timing closure, and collaborate with system engineering to deliver a complete hardware solution.

Qualifications

• 2+ years of FPGA design experience
• Strong Xilinx/AMD Vivado experience
• Verilog/SystemVerilog proficiency
• Advanced FPGA implementation skills (synthesis, timing closure, constraints)

Responsibilities

• Analyzes customer and system requirements to develop architectural approaches and detailed specifications for electronic products.
• Develops high-level and detailed designs consistent with requirements and specifications.
• Validates designs through reviews, testing and analysis to ensure compliance with requirements.
• Collaborates with system engineering and suppliers; supports hardware/software integration and testing.

Skills

FPGA design

Verilog/SystemVerilog

Digital logic design

Synthesis and timing analysis

Education

Bachelor's degree in engineering or related field

Tools

Xilinx Vivado

Place & Route

Job description

Chipton-Ross is seeking 5 Electrical Design and Analysis Engineer 3's for a contract opportunity in El Segundo, CA.

100% onsite

BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE):

• 2+ years of FPGA design experience.
• Strong Xilinx/AMD Vivado experience.
• Verilog/SystemVerilog proficiency.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).

POSITION RESPONSIBILITIES:

Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. Develops high-level and detailed designs consistent with requirements and specifications. Validates designs through various methods of review, testing and analysis. Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements. Supports Supplier Management with make/buy recommendations and other technical services of limited scope. Provides engineering support throughout the lifecycle of the product. Investigates emerging technologies to develop concepts for future product designs to meet projected requirements. Works under general direction.

The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.

The candidate must have experience troubleshooting static timing violations and creating complex designs coded in HDL (not simply instantiating IP blocks). This experience are requirements that will be screened in resume review and interview.

Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system.

PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE):

• 5+ years of FPGA and/or ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency required.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).

REQUIRED EDUCATION:

Minimum of a Bachelor of Science degree from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

WORK HOURS:

Full-Time/First Shift

8:00 AM - 4:30 PM

ADDITIONAL:

Applicants responding to this position will be subject to a government security investigation and must meet eligibility requirements by currently possessing the ability to view classified government information.

This work assignment has been designated as "safety sensitive" by the Client. Contractors assigned to safety sensitive jobs at the Client site must first complete regulatory preplacement requirements prior to reporting to assignment. Additionally, contractors assigned to safety sensitive work will be subject to random drug and alcohol testing in accordance with federal mandates.