Design Engineer (8008)

Taiwan Semiconductor Manufacturing Company Limited; San Jose (CA); On-site; USD 156,000 - 158,000; Full time

Job summary

TSMC Technology, Inc. in San Jose seeks a Design Engineer to drive DRC/LVS/ERC analysis and fix PDV/EMIR/Noise/SigEM issues, while implementing timing ECOs on high‑performance blocks.

The role requires a Master’s in EE or related field and hands‑on experience with Cadence Innovus, Virtuoso, Tempus, and Design Compiler, RTL coding, and chip‑level signoff.

Qualifications

• Experience in VLSI design and digital ICs, RTL coding and testing.
• Strong knowledge of DRC/LVS/ERC and physical verification.
• Familiar with Cadence Innovus, Virtuoso, Tempus and DC workflows.

Responsibilities

• DRC/LVS/ANTENNA analysis and cleanup.
• Implement ECOs for timing closure and clock-tree customization.
• Floorplan analysis, power integrity checks, and place-and-route sign-off.

Skills

VLSI design

RTL coding

Digital design

Design for testing

Clock tree design

Power integrity

Chip integration

Education

Master’s degree in Electrical Engineering or related field

Tools

Cadence Innovus

Cadence Virtuoso

Tempus

Design Compiler (DC)

Job description

Job Title: Design Engineer

Job Description: Responsible for the Design Rule Check, Layout vs. Schematic checking, and fixing all PDV/EMIR/Noise/SigEM violations and errors. Perform customization and implementation of top clocks and timing ECOs on high performance blocks. Specific duties of the position include the following: Specific job duties include: DRC/LVS/ERC/ANTENNA analysis and clean up; Floorplan analysis and congestion solution; Power IR/EM analysis and fix; Signal Em/Noise analysis and fix; Physical verification sign off; Implementing ECOs for timing closure; Customizing Clock tree structure; and Performing floor plan, place, and route.

Requirements: Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field of study.

Work experience must have included: Knowledge of hardware design including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation; knowledge of major EDA tools/design flows including Cadence Innovus; Cadence Virtuoso; Tempus; Design Compiler(DC); Experience in RTL coding, digital design and testing, physical implementation; Experience in Perl/TCL language programming; Experience in N16 and below technology, Chip level integration, and wire editing, Low-power implementation methodology; Experience with Netlist-GDS P&R, signoff task; and Experience in block level implementation or chip integration and signoff.

Work site: TSMC Technology, Inc., 2851 Junction Avenue, San Jose, CA 95134 and various unanticipated work locations

Salary Range: $155,896 to $158,000 per year

Company Description

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC Technology, Inc. may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC Technology, Inc. obtaining any export license or other approval that may be required by the U.S. Government.

Diversity statement

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at [e-mail]. TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case‑by‑case basis.

Pay Transparency / Benefits statement

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role pays a salary range of $155,896 to $158,000/year. The range displayed reflects the minimum target for new hires. Actual pay may be more than the posted wage. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.

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