Design Engineer - VLSI Physical Verification & Timing

TSMC - Taiwan Semiconductor Manufacturing Company Limited; California (MO); On-site; USD 156,000 - 157,000; Full time

Job summary

TSMC - Taiwan Semiconductor Manufacturing Company Limited seeks a Design Engineer in San Jose, CA to handle design rule checks, LVS/ERC, and timing closure tasks for high-performance blocks. Responsibilities include DRC/LVS/ANTENNA analysis, floorplan review, and ECO implementation to meet performance targets.

The role requires a Master’s degree in Electrical or Computer Engineering, along with experience in RTL coding, digital design, and chip-level signoff using major EDA tools.

Qualifications

• Experience in RTL coding, digital design and testing.
• Experience with chip-level integration and signoff tasks.

Responsibilities

• Perform DRC/LVS/ERC/ANTENNA analysis and cleanup.
• Fix Floorplan congestion and power integrity issues.
• Implement ECOs for timing closure and clock customization.

Skills

RTL coding

Digital design

Design verification

Perl/TCL

N16 and below tech

Low-power design

Netlist-GDS P&R

Block-level integration

EDA tools & flows

VLSI design

Education

Master’s degree in Electrical Engineering

Job description

TSMC - Taiwan Semiconductor Manufacturing Company Limited seeks a Design Engineer in San Jose, CA to handle design rule checks, LVS/ERC, and timing closure tasks for high-performance blocks. Responsibilities include DRC/LVS/ANTENNA analysis, floorplan review, and ECO implementation to meet performance targets.

The role requires a Master’s degree in Electrical or Computer Engineering, along with experience in RTL coding, digital design, and chip-level signoff using major EDA tools.