Design Engineer

IC Resources; Irvine (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

IC Resources is seeking a hands-on RTL/SoC engineer to architect, design and verify IP RTL implementations using SystemVerilog for advanced wireless applications. You will contribute to the architecture, verification and documentation while shipping high-throughput electronics.

You will prototype in C/C++/Matlab, optimize timing and resources, and collaborate across engineers, testers and program managers to align with broader product goals and schedules.

Qualifications

• 4+ years of relevant industry experience, degree qualified
• AXI interfacing experience
• Timing and hardware resource optimization for high throughput signal processing
• C/C++/Matlab prototyping for design and verification
• Solid version control practices (Git) and documentation habits (Confluence)

Responsibilities

• Architecture, design, development, verification and documentation of IP RTL implementations using SystemVerilog
• Collaborate with stakeholders across technical and non-technical teams to shape and deliver high-performance wireless IP

Skills

SystemVerilog

AXI interfacing

C/C++

Matlab

Timing optimization

Git

Confluence

Jenkins

Signal processing

Automation

Tools

ModelSim

Quartus

Vivado

Synopsys DC

Cadence Genus

Job description

Join an elite team working at the cutting edge of wireless communications technology, developing IP, system, and board solutions that push the capabilities of 5G forward.

This is a hands on role where you'll play a real part in growing our product portfolio, not just executing someone else's roadmap.

What you'll work on:

Architecture, design, development, verification and documentation of our IP RTL implementations of communication electronics systems using SystemVerilog

What we're looking for:

• 4+ years of relevant industry experience, degree qualified
• EDA tools for simulation and synthesis (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus)
• AXI interfacing experience
• Timing and hardware resource optimization for high throughput signal processing
• C/C++/Matlab prototyping for design and verification
• Solid version control practices (Git) and documentation habits (Confluence)
• Bonus points for EDA tooling admin experience, automation (Jenkins), or knowledge of communications signal processing (error correction, equalization, channel estimation, beamforming)

We're looking for someone highly capable, motivated, and commercially savvy, someone who builds trust quickly and communicates clearly across technical and non technical stakeholders alike.

If you want to help shape the next generation of global wireless connectivity, this is your seat at the table.