Senior Hardware Design Engineer

AccelerComm Ltd; United States; On-site; USD 150,000 - 230,000; Full time

Job summary

AccelerComm Ltd. seeks multiple Senior Hardware Design Engineers to advance space-qualified DSP solutions for 5G base stations on satellites. You will contribute RTL design for FPGA/ASIC, optimize timing and resources, and collaborate across architecture, verification, and physical implementation teams.

Lead the development of high-performance digital blocks, create testbenches, and integrate with the latest FPGA platforms while adhering to engineering processes and documentation standards.

Qualifications

• Proficient in RTL (Verilog/SystemVerilog) for complex ASIC/FPGA products.
• Strong track record delivering digital designs in ASIC/FPGA.
• Experience optimizing timing and hardware resources for high throughput DSP.
• Ability to produce design specifications and verification plans.
• Expert user of EDA tools for simulation and synthesis.

Responsibilities

• Translate requirements into RTL micro-architectures for ASIC/FPGA.
• Create testbenches and implement designs for FPGA and ASIC.
• Deploy designs on FPGA platforms for validation and integration.
• Follow AccelerComm engineering methodology and improve design flow and quality.
• Collaborate across micro-architecture, design, verification and physical implementation teams.

Skills

Verilog/SystemVerilog

ASIC/FPGA design

Timing optimization

Documentation writing

EDA tools

C++/SystemC modelling

High-speed interfaces (PCIe/JESD)

Tools

UVM verification

Job description

Senior Hardware Design Engineer

Department: US Jobs

Employment Type: Permanent

Location: West Coast, United States

Description

We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.

You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions.

Key Responsibilities

As a Senior Hardware Design Engineer, you will:

• Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
• Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
• Deploy your designs onto the latest FPGA development platforms for validation and system integration
• Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
• Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA

Skills, Knowledge and Expertise

Essential:

• Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
• A strong skillset in delivering digital designs in the ASIC and FPGA industry
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Track record in collaborating across teams to produce integrated solutions
• Experience in technical documentation writing – design specifications, user guides, verification plans
• Expert user of EDA tools for simulation and synthesis

Desirable:

• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
• Familiarity with the AMBA bus protocols
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience using C++/SystemC for design modelling and integration
• Experience with high speed interfaces such as PCI-E or JESD
• Knowledge of a scripting language, such as Python
• Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
• Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools