Defect & Yield Optimization Engineer

TSMC - Taiwan Semiconductor Manufacturing Company Limited; Camas (WA); On-site; USD 87,000 - 116,000; Full time

Benefits offered by this job

Health & Wellness

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid Time Off

On-Site Campus Amenities

Job summary

TSMC Washington LLC is seeking a Yield Enhancement Defect Engineer to identify, analyze, and eradicate defect sources that limit wafer yields within a high-volume CMOS fabrication environment. You will leverage metrology, data analytics, and cross-team collaboration to prevent excursions and improve process stability.

Responsibilities include defect reduction, inline inspection ownership, recipe optimization, and customer-facing technical partnership.

Qualifications

• Bachelor’s, Master’s, or Ph.D. in Materials Science, Electrical Engineering, Chemical Engineering, Physics, or related STEM fields.
• Understanding of semiconductor physics, CMOS fabrication, failure analysis, and statistics.
• Strong communication and problem-solving skills.
• SPC knowledge and data analysis helpful.

Responsibilities

• Defect reduction and yield improvement through root-cause analysis and data monitoring.
• Oversee metrology and inline inspection; optimize recipes and SPC usage.
• Collaborate with Fab engineers to isolate tool-induced defects.
• Provide technical support to mixed-signal customers.
• Translate defect metrics into actionable customer-focused insights.

Job description

TSMC Washington LLC is seeking a Yield Enhancement Defect Engineer to identify, analyze, and eradicate defect sources that limit wafer yields within a high-volume CMOS fabrication environment. You will leverage metrology, data analytics, and cross-team collaboration to prevent excursions and improve process stability.

Responsibilities include defect reduction, inline inspection ownership, recipe optimization, and customer-facing technical partnership.