Data Center Post-Silicon Power & Performance Engineer

Qualcomm Incorporated; Austin (TX); On-site; USD 141,000 - 212,000; Full time

Job summary

Qualcomm Technologies, Inc. in Austin, TX, seeks a Data Center Post Silicon Power and Performance Engineer to characterize, debug, and optimize the performance and power of complex SoCs and systems.

You will set up methodologies, develop validation and benchmarking plans, and verify silicon meets performance and power targets. You will collaborate across design, architecture, emulation, firmware, and software teams to optimize workloads, drive tuning strategies, and contribute to next‑gen server

Qualifications

• Bachelor's or Master’s in Engineering, CS, or related field.
• 4+ years of Systems Engineering or related work.
• Experience with post-silicon performance and power analysis.

Responsibilities

• Characterize Data Center workloads on system for pre-Si modeling inputs.
• Define end-to-end performance and power analysis plans for server CPUs.
• Debug issues during pre-silicon, bring-up, validation, and production phases.
• Define optimization strategy for CPU workload performance.
• Lead cross-team test collaborations and track test execution.
• Work with design, architecture, emulation, firmware, DV, and software teams for silicon readiness.
• Develop knowledge of CPU architecture, SoC system architecture, and benchmarking techniques.
• Drive innovations to enhance CPU and system performance and power validation.

Skills

C/C++

Python

Data Center workloads

CPU performance analysis

Debugging

Collaboration

Communication

Education

Bachelor's degree in Engineering or CS

Master's degree in Engineering or CS

PhD in Engineering/CS (optional)

Tools

DAQs

Logic analyzers

Oscilloscopes

Job description

Qualcomm Technologies, Inc. in Austin, TX, seeks a Data Center Post Silicon Power and Performance Engineer to characterize, debug, and optimize the performance and power of complex SoCs and systems.

You will set up methodologies, develop validation and benchmarking plans, and verify silicon meets performance and power targets. You will collaborate across design, architecture, emulation, firmware, and software teams to optimize workloads, drive tuning strategies, and contribute to next‑gen server