Cryogenic CMOS Analog IC Design Engineer

GlobalFoundries; Austin (CA); On-site; USD 85,000 - 202,000; Full time

Job summary

GlobalFoundries seeks an experienced Analog Design Engineer to develop advanced analog and mixed-signal ICs and reusable IP for cryogenic CMOS and quantum systems. You will drive designs from architecture through tapeout and silicon validation, collaborating with technology, PDK, modeling, layout, and test teams.

The role requires 5+ years of relevant IC design experience, strong CMOS analog fundamentals, and ability to lead design reviews while mentoring engineers.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Minimum 5 years of analog or mixed-signal IC design experience.
• Experience with schematic, simulation, layout, DRC/LVS, tapeout and silicon validation.
• Strong CMOS analog design fundamentals and PVT/Monte Carlo analysis.
• Ability to translate results into design improvements.

Responsibilities

• Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP.
• Own circuit development from architecture and transistor-level design through tapeout.
• Analyze circuit performance across process, voltage, temp, including cryogenic tests.
• Collaborate with device modeling and PDK teams on cryogenic development and validation.
• Lead analog layout reviews, ensure device matching and signal integrity.
• Define silicon test structures and characterization plans; correlate data with simulations.
• Mentor engineers and participate in cross-functional design reviews.

Skills

Analog/mixed-signal design

Circuit characterization

Mentoring engineers

Cross-functional collaboration

Design reviews ownership

Education

B.S. in Electrical Engineering or related field

Tools

SPICE

Cadence

DRC/LVS

Python scripting

Job description

GlobalFoundries seeks an experienced Analog Design Engineer to develop advanced analog and mixed-signal ICs and reusable IP for cryogenic CMOS and quantum systems. You will drive designs from architecture through tapeout and silicon validation, collaborating with technology, PDK, modeling, layout, and test teams.

The role requires 5+ years of relevant IC design experience, strong CMOS analog fundamentals, and ability to lead design reviews while mentoring engineers.