CPU STA CAD Engineer: Power, PPA & Automation

Qualcomm; Santa Clara (CA); On-site; USD 199,000 - 298,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking a CPU STA CAD engineer to build and support the world’s best analysis tools and flows for cutting-edge CPU designs, focusing on power, performance and area.

You will work with global CPU physical design teams, collaborate with EDA vendors, and drive ECO timing closures while applying AI techniques to optimize EDA workflows and automate scripts and test collateral.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware/Software/Systems Engineering experience.
• Master's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware/Software/Systems Engineering experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware/Software/Systems Engineering experience.

Responsibilities

• Architect and recommend methodology improvements to ensure silicon has best power, performance and area.
• Maintain, support and debug STA and timing closure (ECO) flows and resolve project-specific issues.
• Collaborate with worldwide CPU physical design teams and provide tool/flow guidance and support.
• Work with EDA vendors to define roadmap and resolve tool issues.

Skills

STA experience

Python scripting

Tcl scripting

CI/CD

Debugging

PPA optimization

EDA tooling

AI in EDA

Synthesis/PnR

Education

Bachelor's degree in Electrical/Computer Engineering/CS

Master's degree in Electrical/Computer Engineering/CS

PhD in Electrical/Computer Engineering/CS

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking a CPU STA CAD engineer to build and support the world’s best analysis tools and flows for cutting-edge CPU designs, focusing on power, performance and area.

You will work with global CPU physical design teams, collaborate with EDA vendors, and drive ECO timing closures while applying AI techniques to optimize EDA workflows and automate scripts and test collateral.