CPU RTL Design Engineer

Intel Corporation; Austin (TX); Hybrid; USD 141,910 - 269,100; Full time

Benefits offered by this job

Competitive compensation package

Stock bonuses

Health and retirement benefits

Job summary

Intel Corporation is looking for a CPU Logic Design Engineer in Austin, Texas. This role focuses on the design and optimization of CPU logic, requiring extensive experience in RTL design and modern power-efficient techniques.

The company offers a competitive compensation package with an annual salary range of $141,910.00–$269,100.00. The position supports a hybrid work model, allowing flexibility between on-site and remote work.

Qualifications

• 7+ years relevant experience in RTL design.
• Experience with low-power design methods.
• Strong knowledge of hardware modeling and logic debug environments.

Responsibilities

• Develop and optimize logic design for the CPU.
• Participate in defining architecture and microarchitecture features.
• Review verification plans to ensure correct validation.

Skills

RTL design using Verilog

Energy-efficient logic design

Cross-clock domain crossings

Scripting languages (TCL, Perl, Python)

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Job description

Intel is a leading technology company focused on silicon innovation and engineering excellence. We develop world‑changing technology and inspire big ideas to build a better tomorrow.

The Role and Impact

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel’s cutting‑edge processors. You will drive the development of register‑transfer level (RTL) code and simulation for the CPU, enabling creation of cell libraries, functional units, and CPU IP blocks for integration into full‑chip designs. Your expertise will shape architecture and microarchitecture features, ensuring Intel delivers innovative solutions that lead the industry in performance, energy efficiency, and design integrity.

Key Responsibilities

• Develop and optimize logic design, register‑transfer level (RTL) coding, and simulation for the CPU.
• Participate in defining the architecture and microarchitecture features of the CPU design.
• Write RTL and optimize logic for power, performance, area, and timing goals.
• Ensure design integrity for physical implementation through effective strategies, tools, and methods.
• Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
• Document microarchitectural specifications (MAS) for CPU features.
• Collaborate with SoC customers to ensure seamless integration and high‑quality performance of the CPU block.

Qualifications

Minimum Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science with 7+ years of relevant experience; OR Master’s degree with 5+ years of experience; OR PhD with 2+ years of experience.
• 7+ years experience in RTL design using Verilog, V2K, or SystemVerilog, with strong knowledge of hardware modeling and logic debug environments.
• 5+ years experience with modern energy‑efficient and low‑power logic design methods, including techniques applicable to high‑frequency optimization.
• 5+ years experience in Cross‑clock domain crossings and power‑aware design.
• 3+ years experience in scripting languages such as TCL, Perl, or Python.

Preferred Qualifications

• Knowledge of CPU power‑management, including power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states, and reset sequence handling.
• Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Experience with high‑speed circuit design and optimization for datapath, circuits, and arrays.
• Familiarity with circuit planning and timing convergence processes.
• Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
• Proficient with static timing analysis, UPF and lint checks.
• Good communication skills.

Job Type

Experienced Hire; Shift: Shift 1 (United States of America); Primary Location: US, Texas, Austin; Additional Locations: US, Arizona, Phoenix.

Benefits

Intel offers a competitive compensation package that includes base salary, stock bonuses, and benefit programs such as health, retirement, and vacation. The annual salary range for U.S. locations is $141,910.00–$269,100.00 USD.

Hybrid Work Model

This role is eligible for a hybrid work model, allowing employees to split time between on‑site and off‑site work.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.