CPU Power Architect — Power-Efficiency Leader (Equity)

NVIDIA Corporation; Santa Clara (CA); On-site; USD 152,000 - 288,000; Full time

Job summary

NVIDIA Corporation in Santa Clara is seeking a skilled CPU Power Architect to drive power efficiency across the design cycle, from architectural modeling through RTL implementation to silicon validation. You will model, estimate, and optimize power, collaborating with software, architecture, RTL, PD, and validation teams to meet aggressive perf‑per‑watt targets.

In this role you will set up power tests, analyze leakage and dynamic power, and validate pre-silicon estimates with silicon data.

Qualifications

• BS/MS in EE, CE, or CS or equivalent experience.
• 5+ years in ASIC power measurement and optimization.
• Strong understanding of leakage and dynamic power in VLSI.
• Experience with RTL and netlist power analysis tools such as Power Artist, PrimeTime PX.
• Familiarity with CPU microarchitecture and its impact on power.

Responsibilities

• Pre-silicon power estimation: Model and estimate CPU power at C-model, RTL, and netlist stages using industry-standard tools.
• Power optimization: Identify inefficiencies and drive design improvements in collaboration with architects, RTL designers, and PD engineers.
• Test development: Create targeted power characterization tests for both simulation and silicon.
• Silicon validation: Set up power measurement equipment and measure CPU power and performance in the lab; correlate silicon results with pre-silicon estimate to refine models.
• Cross-functional collaboration: Partner with multiple engineering disciplines to achieve optimal power efficiency without compromising performance.

Skills

Power analysis

RTL power analysis

VLSI power optimization

Cross-functional collaboration

DVFS / clock gating

Education

BS/MS in EE/CE/CS

Tools

Power Artist

PrimeTime PX

Job description

NVIDIA Corporation in Santa Clara is seeking a skilled CPU Power Architect to drive power efficiency across the design cycle, from architectural modeling through RTL implementation to silicon validation. You will model, estimate, and optimize power, collaborating with software, architecture, RTL, PD, and validation teams to meet aggressive perf‑per‑watt targets.

In this role you will set up power tests, analyze leakage and dynamic power, and validate pre-silicon estimates with silicon data.