CPU Physical Design Automation & Infrastructure Engineer

Qualcomm Innovation Center, Inc.; Santa Clara (CA); On-site; USD 148,000 - 222,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking an experienced CPU Physical Design Infrastructure and Automation Engineer to improve infrastructure and automation for next-generation CPUs.

You will collaborate with PD, CAD, and methodolog y teams to bring up dashboards and design infrastructure across multiple CPU designs. You will develop new prediction models and automation to speed timing, power and area estimations while working with block-level teams to optimize design methods.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware/Software/Systems experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware/Software/Systems experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Responsibilities

• Work with cross functional teams (PD, CAD, Methodology and STA) to bring up design infrastructure and dashboards for multiple CPU designs and domains.
• Work with all block level implementation teams to analyze, implement and improve the optimization method as it pertains to the designs.
• Work on developing new prediction models and automation for quick timing, power and area estimation.

Skills

Scripting TCL

Python

Perl

CSS

HTML

JavaScript

CGI

Synthesis

Place & Route

STA & Signoff

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree in Electrical/Computer Engineering or related field

PhD in Electrical/Computer Engineering or related field

Tools

Synthesis tools

Place & Route tools

Design Signoff tools

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking an experienced CPU Physical Design Infrastructure and Automation Engineer to improve infrastructure and automation for next-generation CPUs.

You will collaborate with PD, CAD, and methodolog y teams to bring up dashboards and design infrastructure across multiple CPU designs. You will develop new prediction models and automation to speed timing, power and area estimations while working with block-level teams to optimize design methods.