CPU Hardware Engineer: Timing, Synthesis & Verification

Qualcomm; Santa Clara (CA); On-site; USD 148,000 - 222,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Hardware Engineer in Santa Clara to plan, design, verify, and test electronic systems across DSP/FPGA domains. The role involves multi-million gate synthesis, constraints for multi-clock domains, and power/area trade-offs.

You will work with cross-functional teams on complex projects, perform TCL scripting, and contribute to verifications and timing analyses to meet performance requirements.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware/Software/Electrical/Systems Engineering experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware/Software/Electrical/Systems Engineering experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Responsibilities

• Experience in handling complex data path oriented multi-million gate synthesis.
• Experience in developing constraints for multi-clock domains timing analysis.
• Good working knowledge in multi-power domain synthesis and structural power checks using CLP.
• Hands-on experience in Formal verification and strong debugging skills.
• Pre-layout STA knowledge and analyzing timing reports and generating timing ECOs.
• Knowledge on trade-offs for timing/area/power/congestion.
• Exposure to TCL scripting in Synthesis/STA.
• Hierarchy STA with Hyperscale is a plus.
• Interact proactively with stakeholders and work as a team.

Skills

Multi-gate synthesis

DC/Genus Fusion

Timing analysis

Formal verification

Power analysis

TCL scripting

Hierarchical STA

Debugging

Stakeholder collaboration

Education

Bachelor's in EE/CE/CS

Master's in EE/CE/CS

PhD in EE/CE/CS

Tools

DC

Genus

Fusion Compiler

Job description

Qualcomm Technologies, Inc. is seeking a Hardware Engineer in Santa Clara to plan, design, verify, and test electronic systems across DSP/FPGA domains. The role involves multi-million gate synthesis, constraints for multi-clock domains, and power/area trade-offs.

You will work with cross-functional teams on complex projects, perform TCL scripting, and contribute to verifications and timing analyses to meet performance requirements.