Senior FPGA‑Based Hardware System Engineer

Qualcomm; San Diego (CA); On-site; USD 116,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA is seeking a Hardware System Design Engineer, Senior Staff, to own board design from schematic capture to verification testing.

You will drive system architecture with customers and software/firmware teams, handling 10 Gbps+ SERDES designs and memory subsystems. The role requires hands-on lab bring-up, cross-functional collaboration, and mentoring junior engineers.

Qualifications

• Experience with board design: schematic capture, PCB stack-up, 26+ layer layouts, BOM management, verification testing.
• Experience with FPGA board design (Xilinx/Altera).
• HDL coding experience.
• Experience with 10 Gbps SERDES and high-speed I/O designs.
• Power and signal integrity simulations for high-speed designs.
• Familiarity with high-speed design concepts and DFM/DFT considerations.
• Ability to lead design reviews and mentor engineers.

Responsibilities

• Own board design lifecycle from schematic to verification testing.
• Drive system architecture with customers and software/firmware teams.
• Perform SI/PI simulations for high-speed interfaces and recommend changes.
• Lead FPGA board design including memory subsystems.
• Direct lab bring-up and debug of boards and multi-board systems.
• Collaborate with mechanical, layout, and manufacturing teams.

Skills

Board design

Signal integrity

FPGA design

DDR3/DDR4/DDR5 memory

10 Gbps SERDES

Schematic capture

PCB layout

Power integrity

Lab bring-up

Education

Bachelor's or Master’s in Electrical/Electronics Engineering

PhD (optional)

Tools

Mentor DxDesigner/Expedition

Vivado

Quartus

HyperLynx

Sigrity PowerSI/PowerDC

ADS

Ansys HFSS

SPICE

Job description

Qualcomm Technologies, Inc. in San Diego, CA is seeking a Hardware System Design Engineer, Senior Staff, to own board design from schematic capture to verification testing.

You will drive system architecture with customers and software/firmware teams, handling 10 Gbps+ SERDES designs and memory subsystems. The role requires hands-on lab bring-up, cross-functional collaboration, and mentoring junior engineers.