CPU Custom Memory Design - SRAMs and Register Files

NUVACORE; Santa Clara (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

NuvaCore is seeking a Custom Memory Design Engineer to drive SRAM and register file memories from schematic development through PDV and signoff. You will partner with Foundry, CAD, RTL, and DFT teams to optimize PPA and ensure robust memory IP across process corners.

You will own end-to-end memory signoff, define memory timing, power and noise models, and help shape design flows and tooling to raise efficiency. Strong collaboration and communication are essential.

Qualifications

• BS or MS in electrical engineering with 8+ years in custom memory design.
• Hands-on transistor-level design for SRAMs and register files on advanced CMOS nodes.
• Experience with SPICE, memory margins, and end-to-end signoff (DRC/LVS/antenna).
• Proven production-grade memory IP tape-out with silicon-validated PPA.

Responsibilities

• Own schematic development and characterize custom memories (SRAM, register files).
• Supervise layout implementation and PDV closure, macro floor planning and critical routing.
• Own end-to-end memory IP signoff: schematic, layout, extraction, and timing/power/noise models.
• Collaborate with RTL, Foundry/PDK, CAD, and DFT teams to optimize memory IP and PPA.
• Define and drive memory design tools, flows, and methodology to raise efficiency.

Skills

Custom memory design

Schematic development

Layout supervision

PPA optimization

Team collaboration

Education

BS or MS in Electrical Engineering

Tools

SPICE

EDA tools

Liberty/CCS

Tape-out tooling

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.

THE ROLE

As a Custom Memory Design Engineer, you will participate in the following :

• Own schematic development and characterize custom memories (SRAM, register files) to optimize PPA at advanced process nodes.
• Supervise layout implementation, defining macro floor planning, critical routing specifications, and driving physical design verification (PDV) closure.
• Own end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization (timing, power, and noise in Liberty/CCS format) across PVT corners, meeting target PPA commitments.
• Partner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize custom memories for downstream design PPA.
• Collaborate closely with RTL, providing explicit custom memory functional specifications, timing behaviors, and state definitions to support accurate RTL modeling.
• Define and drive adoption of Tools, Flows, and Methodology (TFM) — including characterization automation and compiler QA — to raise design efficiency and set team-wide best practices.

MINIMUM QUALIFICATIONS

• Hold a BS or MS degree with 8+ years of experience in custom memory circuit design - SRAMs, and/or Register files.
• Hands-on transistor-level circuit design experience with combo cells, sequential logic in static/dynamic logic families, as well as memory arrays — bit cells, sense amps, decoders — in advanced CMOS nodes.
• Deep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cells architecture.
• Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom memory design workflows.
• Demonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.
• Deep understanding of end-to-end signoff for custom memories — DRC/LVS/antenna, extraction, Spice margins, STA, EM/IR — and characterization flows spanning timing, power, and noise.
• Well-versed in STA and Liberty/CCS lib model development and correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.
• Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.

REQUIREMENTS — PREFERRED

• Substantial experience across the full embedded memory design flow — architecture, circuit design, physical implementation, compiler automation, characterization, and timing/model generation.
• Experience designing and optimizing complex memory sub-blocks (self timed design tracking loops, read/write assist schemes, power-gating headers) and translating PDK device characteristics into cell/bit-cell circuit decisions.
• Proven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.
• Demonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation (cosim) methods.
• Experience partnering directly with foundries on PDK bring-up and device co-optimization (DTCO) at leading-edge nodes.
• Proficient in Python, Perl, or TCL to build and improve design, characterization, and QA automation.
• Experience using Agentic AI tools for productivity and automation.

$140,000 - $200,000 a year