CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading technology company seeks an experienced CPU Microarchitect/RTL Engineer in Beaverton, Oregon. This role involves micro-architecture development, RTL design, and performance exploration for high-performance microprocessors. The ideal candidate will have a Bachelor’s degree and over 10 years of industry experience, particularly in microprocessor architecture and logic design principles. The position offers an opportunity to work at the forefront of technology within a collaborative engineering team.

Qualifications

• BS degree and 10+ years of relevant industry experience.
• Experience with microprocessor architecture and logic design.
• Experience in RTL design and debugging.

Responsibilities

• Develop and specify micro-architecture from high-level exploration.
• Own RTL design and refine it to meet performance goals.
• Support verification team with test bench development.

Skills

Microprocessor architecture

Logic design principles

Verilog

VHDL

Performance exploration

C/C++ programming

Perl or Python

Education

Bachelor's degree in Engineering or related field

Tools

Simulators

Job description

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced technical leader to drive architecture and RTL development of CPU front-end and/or out-of-order subsystem for our performant cores.

Description

• Micro-architecture development and specification – from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership – development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification – support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation – explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery – work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience with microprocessor architecture
• Experience with logic design principles with timing and power implications
• Experience in Verilog or VHDL
• Experience with simulators and waveform debugging process

Preferred Qualifications

• Expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling, register renaming, out-of-order execution
• Understanding of low power microarchitecture techniques
• Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
• Experience in C or C++ programming
• Experience using an interpretive language such as Perl or Python

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