Computer Aided Design Engineer

QUORE IT : Talent Sourcing & Recruitment; Los Altos (CA); Hybrid; USD 250,000 - 350,000; Full time

Benefits offered by this job

Equity

Hybrid work

Job summary

QUORE IT : Talent Sourcing & Recruitment represents a client building AI-powered EDA tooling for optimizing power, performance, and area in semiconductor physical design.

Join a founding team of renowned experts tackling the hardest chip-design problems. You will own meaningful tool-building work, collaborate with major semiconductor customers, and contribute to high-impact projects from day one.

Qualifications

• 2-7 years of experience in VLSI physical design or EDA tool development.
• Experience building EDA tools (not just running scripts).
• Algorithmic/optimization skills (not just scripting).
• Wants to build tools, not just use them.
• BS/MS/PhD in EE, Computer Engineering, or CS.

Responsibilities

• Implement complex design rules from major foundries into the client's AI-powered physical design optimization system.
• Build EDA software tools focused on place and route, PPA optimization, and backend IC implementation.
• Work directly with top-tier semiconductor customers weekly, owning large pieces of customer-facing deliverables.
• Contribute to tactical feature development (closing gaps, fixing bugs, shipping features) and strategic projects (agentic flows, pre-trained model integration).
• Collaborate with a small, elite team of PhDs and engineers to push the boundaries of what's possible in AI-driven chip design.

Skills

VLSI design

EDA tool development

Algorithmic optimization

Tool building

Education

BS/MS/PhD in EE, Computer Engineering, or CS

Tools

EDA tools

Job description

Compensation:

Base Salary $250K - $350K + Competitive Equity

Why you should join

• The client uses AI to optimize power, performance, and area in physical chip design — solving problems humans literally can't solve alone. They're the only startup tackling PPA optimization in physical design with this approach.
• Founded by a former Google exec (led 600-person teams) and a world-renowned UT Austin professor with 500 research papers. $6M pre-seed closed in March with another round coming in September. Already partnered with GlobalFoundries and working with top semiconductor companies.
• EDA/CAD Engineer role with $250k–$350k salary + 0.01–1.5% equity. Hybrid in Los Altos (Mon–Thu on-site). Hiring 3–7 engineers — ground-floor opportunity at a company with 5 people today.

Required:

• 2 - 7 years of experience in VLSI physical design or EDA tool development
• Experience building EDA tools (not just running scripts)
• Algorithmic/optimization skills (not just scripting)
• Wants to build tools, not just use them
• BS/MS/PhD in EE, Computer Engineering, or CS

Must Have:

• Hands- on place & route or physical design R&D
• Proficiency with industry- standard EDA tools and flows
• Experience at advanced process nodes (7nm and below)
• Degree from a strong engineering program

Nice to Have:

• Worked at Synopsys, Cadence, Intel, Nvidia, or similar

Red Flags:

• 20+ years at one big company (likely too rigid)
• Only frontend/RTL experience with no backend exposure
• Pure script- runner with no interest in algorithms/optimization

About the role

We are looking for an EDA/CAD Engineer with 2-7 years of experience to join the client and help build AI-powered tools that optimize power, performance, and area in semiconductor physical design. You'll be joining a founding team led by world-renowned experts in EDA and VLSI CAD who are tackling the hardest problems in chip design at a seminal moment — Moore's Law is ending, and AI offers a once-in-a-generation opportunity to transform the industry. This is a high-ownership role where you'll work directly with major semiconductor customers (including GlobalFoundries) and have a meaningful impact from day one. We need someone who deeply understands how chips are built and is passionate about writing tools to optimize the design process.

What will you be doing?

• Implementing complex design rules from major foundries into the client's AI-powered physical design optimization system
• Building EDA software tools focused on place and route, PPA optimization, and backend IC implementation
• Working directly with top-tier semiconductor customers every week, owning large pieces of customer-facing deliverables
• Contributing to both tactical feature development (closing gaps, fixing bugs, shipping features) and strategic projects (agentic flows, pre-trained model integration)
• Collaborating with a small, elite team of PhDs and engineers to push the boundaries of what's possible in AI-driven chip design

Cadence, Synopsys, Python, Tcl, Perl, Place and Route Tools, Physical Design Tools, DRC