Compiler Engineer — Frontend for ML-to-Hardware

BoolSi Inc.; Boston (MA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Factorio megabase screenshot

Job summary

BoolSi Inc. seeks a Compiler Engineer to own and expand the front-end that translates high-level C/C++/Rust programs into hardware-ready representations. You will collaborate with ML and hardware teams to ensure safe lowering and clean handoff to silicon.

You will build analysis, fuzzers, and transformations, working with LLVM/MLIR, and engaging with FPGA/HLS workflows to enable scalable hardware acceleration for software developers.

Qualifications

• Strong C and C++ with deep language semantics and UB awareness.
• Hands-on compiler internals experience (LLVM, GCC, MLIR).
• Solid knowledge of SSA, dataflow, CFGs, and abstract interpretation.
• Experience building tools that read and rewrite real code (instrumentation, fuzzers).
• Familiarity with FPGA or HLS flows; ability to hand work to hardware teams.
• Open-source compiler contributions are a plus.

Responsibilities

• Grow the front-end to handle more language features and patterns.
• Analyze and prove properties of user functions and what they touch.
• Build white-box fuzzers and data-generation harnesses for training signals.
• Design program transformations and reshape code for model convergence.
• Extract and operate on program representations (CFGs, DFGs, IR).
• Define contracts with ML team and computer architects for clean compiles.

Skills

Strong C and C++

Compiler internals

SSA / dataflow

Program analysis

Instrumentation & fuzzers

Open-source contributions

FPGA / HLS familiarity

Debugging

Software-hardware boundary

Education

B.S. in CS/CE/EE

Tools

LLVM

GCC

MLIR

Vivado

Vitis HLS

Job description

BoolSi Inc. seeks a Compiler Engineer to own and expand the front-end that translates high-level C/C++/Rust programs into hardware-ready representations. You will collaborate with ML and hardware teams to ensure safe lowering and clean handoff to silicon.

You will build analysis, fuzzers, and transformations, working with LLVM/MLIR, and engaging with FPGA/HLS workflows to enable scalable hardware acceleration for software developers.