Cloud-Scale Physical Design Engineer – ML Inference

Amazon Web Services (AWS)

Cupertino (CA)

On-site

USD 157,300 - 212,800

Full time

14 days+

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Benefits offered by this job

Health insurance
401(k) matching
Paid time off
Parental leave

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA, is seeking a senior hardware/IC design engineer to drive block physical implementation, RTL2GDS flows, and PPA improvements in data center infrastructure.

You will collaborate with RTL, package design, and DFT teams, evaluate new EDA tools, and create dashboards for project tracking while delivering high performance at low cost. This fast-paced role requires leadership, strong sign-off experience, and a track record of timing-closed designs that meet

Qualifications

  • Bachelor's degree in Electrical Engineering or a related field.
  • Experience with RTL to GDSII flows.
  • Strong knowledge of sign-off activities for timing and physical verification.

Responsibilities

  • Drive block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
  • Develop cloud infrastructure to support physical design work.
  • Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvement.
  • Create Dashboard/central reports for project tracking and visualizing QoR/stats
  • Interface directly with RTL, Package Design, DFT and other teams to improve methodologies and efficiencies and drive efforts to resolution.
  • Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, etc.

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence
Mentor Graphics
Synopsys

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA, is seeking a senior hardware/IC design engineer to drive block physical implementation, RTL2GDS flows, and PPA improvements in data center infrastructure.

You will collaborate with RTL, package design, and DFT teams, evaluate new EDA tools, and create dashboards for project tracking while delivering high performance at low cost. This fast-paced role requires leadership, strong sign-off experience, and a track record of timing-closed designs that meet

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