CAD Back-end Lead

Velaura; Santa Clara (CA); On-site; USD 180,000 - 290,000; Full time

Job summary

Velaura is seeking a CAD Back-end Lead to build, integrate, and support design flows used by Custom Design and Physical Design teams. You will own CAD framework development, EDA tool integration from Cadence, Synopsys, Siemens EDA, Ansys, and other vendors, and drive automation and AI-assisted workflows at scale.

The role requires deep ASIC flow expertise, scripting skills, and experience delivering reproducible production environments across advanced-node technologies.

Qualifications

• Must understand ASIC development lifecycle and back-end CAD workflows.
• Experience integrating EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and others.
• Hands-on software development and scripting across Python, Tcl, Bash, Perl, or similar.

Responsibilities

• Develop, integrate, qualify, release, and support CAD flows for custom design and physical verification.
• Own and develop reusable CAD frameworks for custom design, layout, and full-chip implementation.
• Integrate and qualify foundry PDKs, technology files, libraries, and extraction decks.
• Establish source-control and release-management practices using Git, GitLab, Perforce, or equivalent.

Skills

Python

Tcl

Bash

Perl

Git

CI/CD

Automation

AI tooling

Linux

Scripting

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence Virtuoso

Cadence Innovus

Cadence Voltus

Cadence Quantus

Synopsys Fusion Compiler

Synopsys PrimeTime

Synopsys StarRC

Synopsys HSPICE

Synopsys PrimeSim

Siemens Calibre

Ansys RedHawk-SC

Job description

Role Overview

We are looking for a CAD Back-end Lead to build, integrate, and support the design flows used by Velaura’s Custom Design and Physical Design teams. This role will own the CAD framework supporting custom design, parasitic extraction, circuit simulation, characterization, physical implementation, timing and power analysis, physical verification, and tapeout.

You will work closely with Custom Circuit Design, Custom Layout, Characterization, Physical Design, STA, Power Integrity, Physical Verification, and CAD Infrastructure teams to translate domain-specific methodologies into qualified, scalable, and reproducible production flows.

The functional teams will own design methodology, execution, QoR targets, and signoff criteria. This role will own flow architecture, EDA tool integration, automation, version control, release qualification, regression infrastructure, documentation, and production support.

The ideal candidate combines a strong understanding of custom-design and back-end workflows with hands-on expertise in EDA integration, software development, scripting, regression automation, agentic AI development, and advanced-node enablement. Success in this role will be measured by flow reliability, ease of use, turnaround time, reproducibility, and engineering productivity.

Responsibilities

• Develop, integrate, qualify, release, and support CAD flows spanning Custom Design, physical implementation, and Physical Verification across multiple projects and advanced process technologies.

• Own and develop reusable CAD frameworks for custom design and custom layout, as well as block-level, hierarchical, subsystem-level, and full-chip physical implementation.

• Integrate EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and other vendors into consistent, version-controlled, and reproducible design environments.

• Partner with domain experts to translate Custom Design, Characterization, Physical Design, STA, Power Integrity, and Physical Verification methodologies into automated production flows.

• Integrate and qualify foundry PDKs, technology files, standard-cell libraries, memories, IP collateral, RC corners, extraction decks, signoff rule decks, and EDA tool configuration files.

• Own back-end flow releases, including configuration management, regression testing, qualification, documentation, deployment, versioning, and rollback.

• Establish source-control and release-management practices using Git, GitLab, Perforce, or equivalent platforms, including branching, tagging, code reviews, release baselines, and change tracking.

• Build regression infrastructure to validate flow functionality, EDA tool upgrades, PDK updates, methodology changes, and design collateral before production deployment.

• Develop automated quality checks and dashboards covering flow status, runtime, resource usage, failures, design quality, and key QoR metrics.

• Work with central CAD and Infrastructure teams on compute requirements, job scheduling, storage, EDA tool deployment, license usage, and capacity planning for Custom Design and back-end workloads.

• Partner with foundries, IP providers, and EDA vendors to resolve issues involving EDA tools, PDKs, technology files, rule decks, and design methodologies.

• Evaluate new EDA technologies based on measurable improvements in quality of results, turnaround time, scalability, reliability, engineering productivity, and cost.

• Actively use AI-assisted coding and engineering tools for software development, test generation, code review, documentation, log analysis, debugging, and flow optimization.

• Architect and develop agentic AI workflows for EDA flow orchestration, regression monitoring, failure classification, root-cause analysis, QoR comparison, knowledge retrieval, and production support.

• Integrate AI agents with EDA tools, job schedulers, version-control systems, regression databases, dashboards, and internal engineering knowledge repositories.

• Establish appropriate security, access-control, IP-protection, validation, and human-approval mechanisms for applying AI to proprietary design data and production EDA environments.

• Define measurable success criteria for AI-assisted workflows and transition successful prototypes into qualified production use.

• Establish coding standards, code-review practices, validation requirements, documentation standards, and release processes for back-end CAD development.

• Mentor CAD engineers and promote strong practices in software development, automation, version control, regression testing, agentic AI development, and production flow support.

Required Qualifications

• Deep understanding of the ASIC development lifecycle, with strong knowledge of custom design, physical implementation, signoff, Physical Verification, and tapeout flows.
• Experience developing and supporting CAD flows across multiple successful ASIC or SoC programs.
• Experience integrating EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and/or other major EDA vendors.
• Familiarity with tools such as Cadence Virtuoso, Innovus, Voltus, and Quantus; Synopsys Fusion Compiler, PrimeTime, StarRC, HSPICE, and PrimeSim; Siemens Calibre; and Ansys RedHawk-SC.
• Experience integrating foundry PDKs, technology files, timing libraries, physical libraries, extraction decks, verification rule decks, and third-party IP collateral.
• Strong software-development and scripting skills using Python, Tcl, Bash, Perl, or similar languages.
• Hands-on experience with version-control and collaboration platforms such as Git, GitLab, Perforce, or equivalent tools.
• Experience with branching, tagging, merge requests, code reviews, release baselines, configuration management, and rollback strategies.
• Experience with automated regression testing, continuous integration, release management, and reproducible engineering practices.
• Hands-on experience using modern AI coding assistants and engineering tools as part of software or CAD flow development.
• Experience developing AI-oriented or LLM-based applications or agentic workflows that integrate tools, APIs, engineering data, and knowledge sources.
• Ability to validate AI-generated code, analysis, and recommendations before deployment in production semiconductor design flows.
• Practical understanding of data security, access control, confidentiality, and IP protection when applying AI to proprietary engineering environments.
• Strong understanding of Linux environments, distributed compute, batch scheduling, storage systems, and license-dependent EDA workloads.
• Strong debugging and root-cause-analysis skills across EDA tools, scripts, design databases, PDK collateral, and compute environments.
• Experience supporting production design teams and resolving time-critical flow issues during major project milestones and tapeout.
• Excellent communication skills and the ability to collaborate with global Custom Design, Physical Design, STA, Power Integrity, Physical Verification, CAD, foundry, and EDA- vendor teams.

Preferred Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, Computer Science, or a related discipline.
• Experience enabling leading-edge FinFET or Gate-All-Around process technologies.
• Experience building QoR dashboards, regression analytics, flow-monitoring systems, or automated failure-triage solutions.
• Experience deploying production-quality agentic AI workflows for semiconductor design, EDA automation, regression triage, design-data analysis, or engineering knowledge management.
• Experience developing and scaling CAD capabilities in a fast-paced or early-stage semiconductor company.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: [e-mail]. This contact
information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case-by-case basis.