CAD Engineer – Physical Design Verification & Flows

Micron; Richardson (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Micron Technology, Inc. is seeking a Memory Design Group CAD Engineer to design, debug, and optimize CMOS layout flows and EDA tools. You will collaborate with design and verification teams worldwide to improve cost, quality, reliability, and time-to-market for memory products.

You will evaluate tools, develop flows, and provide training to enable end users while advancing next-generation CAD software and infrastructure to increase productivity across memory designs.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• 5+ years of industry experience in CAD/EDA for CMOS design.
• Strong Unix and shell scripting fundamentals.
• Good knowledge of CMOS circuits and physical design rules.

Responsibilities

• Develop tools, flows, and methodologies to increase productivity of memory designs.
• Integrate commercial EDA tools into design flows.
• Provide training and documentation to end users on new tools and methods.
• Research and develop next-generation CAD software for product needs.
• Identify deficiencies and improve tool flows for efficiency and cost.
• Support engineering infrastructure and collaborate with design, layout, verification teams.

Skills

Unix scripting

Python

Verilog basics

Shell scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

Tools

Calibre DRC/LVS

Cadence Virtuoso SKILL

Verilog-A

HSPICE

VCS

SPF extraction

Python Qt

ncverilog

Job description

Micron Technology, Inc. is seeking a Memory Design Group CAD Engineer to design, debug, and optimize CMOS layout flows and EDA tools. You will collaborate with design and verification teams worldwide to improve cost, quality, reliability, and time-to-market for memory products.

You will evaluate tools, develop flows, and provide training to enable end users while advancing next-generation CAD software and infrastructure to increase productivity across memory designs.