Senior CAD Engineer — Memory Design & Flows

Micron; Richardson (TX); Sur place; USD 110 000 - 190 000; Plein temps

Avantages offerts par ce poste

Medical, dental and vision plans

Paid time off

Paid holidays

Résumé du poste

Micron Technology, Inc. is seeking a Memory Design Group CAD Engineer to enhance and debug in-house and commercial EDA tools, enabling efficient CMOS layout and design workflows. You will collaborate with design and verification teams globally to ensure cost, quality, reliability, and timely market delivery.

The role emphasizes evaluating tools, improving flows, and providing training while supporting cross-functional teams across memory design, layout, and process disciplines.

Qualifications

• Strong programming fundamentals with Unix shell scripting experience.
• Solid knowledge of CMOS circuits, submicron physical design rules, and layout design rules.
• Experience with layout flows (Calibre DRC/LVS, floorplanning, automated P&R, SPF extraction).
• Experience with RTL-to-GDS flows and EDA toolchains including Verilog, Verilog-A, ncverilog, VCS, Spice/FastSpice, HSPICE.

Responsabilités

• Develop tools, flows, and methodologies to increase productivity of Memory designs.
• Integrate commercial EDA tools into design flows.
• Provide training, documentation, and support on new tools and methods.
• Collaborate with design, layout, verification, and process teams.
• Research and develop next-gen CAD software to meet product needs.
• Identify deficiencies in current tools and flows and propose improvements.
• Understand EDA industry tools and trends to improve efficiency and cost.
• Evaluate tools with internal customers and define improvement flows.
• Develop, maintain, and support engineering infrastructure.

Connaissances

Unix shell scripting

Verilog

Python

Cadence SKILL

CMOS design basics

Formation

Bachelor’s or Master’s degree in CE/EE/EECS

Outils

Calibre DRC/LVS

Verilog/VCS tools

HSPICE/Spice simulators

Cadence Virtuoso

Description du poste

Micron Technology, Inc. is seeking a Memory Design Group CAD Engineer to enhance and debug in-house and commercial EDA tools, enabling efficient CMOS layout and design workflows. You will collaborate with design and verification teams globally to ensure cost, quality, reliability, and timely market delivery.

The role emphasizes evaluating tools, improving flows, and providing training while supporting cross-functional teams across memory design, layout, and process disciplines.