ASIC STA Engineer

Anysilicon; Maynard (MA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Acacia, part of Cisco, seeks an ASIC Design Engineer on the STA team to advance high‑speed optical interconnects that scale networks. You will collaborate with cross‑functional teams to meet timing, performance, and quality goals.

Responsibilities include developing STA methodologies and checklists, solving timing and flow issues, and driving execution to maintain progress and accuracy in STA processes using Verilog/SystemVerilog.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 5+ years of ASIC Design experience, or a Master's degree with 3+ years, or a PhD with no experience required.
• Experience with Verilog/SystemVerilog programming.

Responsibilities

• Develop methodologies, guidelines, and checklists to streamline static timing analysis (STA) work.
• Resolve design and flow issues to ensure project success.
• Drive execution to maintain progress and accuracy in STA processes.

Skills

Communication skills

STA experience

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD

Job description

Join Acacia, part of Cisco, as an ASIC Design Engineer on the STA team, where you will contribute to the development of high-speed optical interconnect products that enhance network scalability. This role involves working closely with cross-functional teams to innovate and solve challenges in next-generation optical interconnects, all while being part of a company recognized as one of the best workplaces globally.

Responsibilities:

• Develop methodologies, guidelines, and checklists to streamline static timing analysis (STA) work.
• Resolve design and flow issues to ensure project success.
• Drive execution to maintain progress and accuracy in STA processes.

Qualifications:

• Bachelor's degree in Electrical or Computer Engineering with 5+ years of ASIC Design experience, or a Master's degree with 3+ years of experience, or a PhD with no experience required.
• Experience with Verilog/SystemVerilog programming.

Skills:

• Strong written and verbal communication skills.
• Prior experience in static timing analysis (STA) is preferred.