ASIC/SoC Hardware Design Engineer (5G & Wireless)

Boulder Connect

San Diego (CA)

On-site

USD 110,000 - 190,000

Full time

3 hours ago
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Job summary

Boulder Connect is seeking a Hardware Design Engineer focused on developing high‑performance wireless and 5G chipsets for mobile, IoT, and automotive applications. You will architect, design, and verify digital and mixed‑signal blocks, create schematics, perform simulations, and support lab bring‑up and validation.

You will collaborate with RF, firmware, and physical design teams to optimize performance, power, and area, prepare design documentation, conduct timing and signal‑integrity analysis,

Qualifications

  • Experience in hardware design, simulation, and verification.
  • Strong knowledge of digital and mixed-signal hardware development.
  • Ability to collaborate across multidisciplinary teams to optimize designs.
  • Proficiency in design documentation and debugging silicon issues.

Responsibilities

  • Architect, design, and verify digital and mixed-signal hardware blocks.
  • Create schematics, perform simulations, and support lab bring-up and validation.
  • Collaborate with RF, firmware, and physical design teams to optimize performance, power, and area.
  • Prepare design documentation, conduct timing and signal-integrity analysis, and debug silicon issues.
  • Support productization in a fast-paced, innovation-driven environment.

Skills

Digital design
Mixed-signal design
Simulation & verification
Schematic capture
Lab bring-up
Cross-functional collaboration

Job description

Boulder Connect is seeking a Hardware Design Engineer focused on developing high‑performance wireless and 5G chipsets for mobile, IoT, and automotive applications. You will architect, design, and verify digital and mixed‑signal blocks, create schematics, perform simulations, and support lab bring‑up and validation.

You will collaborate with RF, firmware, and physical design teams to optimize performance, power, and area, prepare design documentation, conduct timing and signal‑integrity analysis,

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