ASIC PDN & EMIR Engineer - Power Integrity, Tapeout Ready

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 150,000 - 225,000; Full time

Job summary

APPLE INC in Cupertino, California is seeking a Hardware / PDN design engineer to debug flow issues and enhance ASIC power delivery networks. You will work across floor planning, clock and power distribution, and run analyses with industry tools to validate chip-level PDN reliability.

The role involves close collaboration with CAD/technology and implementation teams through the full design cycle to drive tape-out sign-off, with an emphasis on static/dynamic power, EM/Noise analyses, scripting

Qualifications

• Bachelor’s degree in Electrical Engineering, Mechatronic Engineering, or related field.
• Experience designing, simulating, and validating large SOC PDN in advanced process nodes.
• Experience with static and power analysis tools like RedHawk or Voltus.

Responsibilities

• Debug flow related issues and enhancements in ASIC PDN design.
• Work with ASIC physical design including floor planning, clock and power distribution.
• Perform analyses with industry tools such as RedHawk, Voltus, ETS, and PT-SI.
• Collaborate with CAD/technology teams for flow bring up and validation; signoff for tapeout.

Skills

Power analysis

PDN design

Static power analysis

Dynamic power analysis

EMIR debugging

Scripting (Python, Tcl, Perl)

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

Ansys RedHawk

Cadence Voltus

Job description

APPLE INC in Cupertino, California is seeking a Hardware / PDN design engineer to debug flow issues and enhance ASIC power delivery networks. You will work across floor planning, clock and power distribution, and run analyses with industry tools to validate chip-level PDN reliability.

The role involves close collaboration with CAD/technology and implementation teams through the full design cycle to drive tape-out sign-off, with an emphasis on static/dynamic power, EM/Noise analyses, scripting