Senior ASIC & FPGA Layout Engineer (Analog/Mixed-Signal)

Anysilicon; Orlando (FL); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Lockheed Martin in Florida is seeking an experienced ASIC & FPGA Design Engineer to own the layout flow from floorplan to tape out. You will collaborate with circuit designers to produce high-performance, parasitic-aware physical designs for advanced defense systems.

The role requires 8+ years in full-custom analog or mixed-signal IC layout, proficiency with 130nm–12nm processes, and experience with Synopsys Custom Compiler and Cadence Virtuoso. A U.S.

Qualifications

• Experience with full-custom analog or mixed-signal IC layout design.
• Ability to perform EMIR analysis and address IR drop and electromigration.
• Familiarity with layout automation and scripting (Python, Tcl, or Perl).

Responsibilities

• Own the entire layout flow from floorplan through tape out.
• Collaborate with circuit designers to create high-performance, parasitic-aware physical designs.
• Create floorplans and optimize area, matching, signal integrity, and power delivery for analog blocks.
• Drive DRC, LVS, and ERC verification for full closure across multiple foundries.
• Perform EMIR analysis to address IR drop and electromigration issues.
• Develop and maintain layout methodology and automation scripts.
• Manage tape out sign-off packages, including documentation and design rule decks.
• Mentor junior layout engineers and foster a knowledge-sharing culture.

Job description

Lockheed Martin in Florida is seeking an experienced ASIC & FPGA Design Engineer to own the layout flow from floorplan to tape out. You will collaborate with circuit designers to produce high-performance, parasitic-aware physical designs for advanced defense systems.

The role requires 8+ years in full-custom analog or mixed-signal IC layout, proficiency with 130nm–12nm processes, and experience with Synopsys Custom Compiler and Cadence Virtuoso. A U.S.