ASIC/FPGA Design Co-op: Digital IP & Verification

Ciena Corporation; Town of Victor (NY); On-site; USD 37,000 - 51,000; Full time

Benefits offered by this job

Employee Assistance Program (EAP)

Company-paid holidays

Paid sick leave

Vacation pay

Job summary

Ciena Corporation in the United States is seeking a student for a 4-month term starting January 2027 to join the ASIC IP team, contributing to the design and verification of client protocol mapping IP used in WaveLogic coherent engine chipsets.

This role provides hands-on exposure to digital ASIC development, verification methodologies, prototype development, automation, and optical networking technologies.

Qualifications

• Actively enrolled in a Bachelor's degree program in Electrical Engineering or Computer Engineering.
• Prior ASIC or FPGA development experience is preferred.
• Strong knowledge of SystemVerilog, Verilog, VHDL and Python; good technical writing skills.

Responsibilities

• Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation.
• Collaborate with design and verification engineers on client subsystem and core development activities.
• Implement digital designs using SystemVerilog, Verilog, and VHDL.
• Verify digital designs using SystemVerilog and UVM methodologies.
• Develop and enhance prototype and development automation solutions.
• Apply communications standards knowledge within development activities.

Skills

SystemVerilog

Verilog

VHDL

Python

Digital design

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

Ciena Corporation in the United States is seeking a student for a 4-month term starting January 2027 to join the ASIC IP team, contributing to the design and verification of client protocol mapping IP used in WaveLogic coherent engine chipsets.

This role provides hands-on exposure to digital ASIC development, verification methodologies, prototype development, automation, and optical networking technologies.