ASIC/FPGA Design Co-op - Client Protocols & Verification

Ciena Corporation; New York (NY); On-site; USD 37,000 - 52,000; Part time

Benefits offered by this job

Employee Assistance Program

Company-paid holidays

Sick leave and vacation pay

Job summary

Ciena invites students to join the ASIC IP team for a 4-month co-op starting January 2027 in New York. You will design and verify digital blocks for key WaveLogic chipsets and participate in FPGA-based validation.

The role offers exposure to automation, prototype development, and collaboration across engineering teams. Ideal candidates are actively enrolled in EE/CE, have ASIC/FPGA experience, and are proficient in SystemVerilog, Verilog, VHDL, and Python.

Qualifications

• Actively enrolled in a Bachelor's degree program in Electrical Engineering or Computer Engineering.
• Experience with ASIC or FPGA development is required.
• Knowledge of SystemVerilog, Verilog, VHDL and Python is essential.
• Strong verbal and technical writing skills; able to work independently or in a team.

Responsibilities

• Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA validation.
• Collaborate with design and verification engineers on client subsystem and core development.
• Implement digital designs using SystemVerilog, Verilog, and VHDL; verify with SystemVerilog and UVM.
• Develop prototype and development automation solutions; apply standards in development activities.

Skills

SystemVerilog

Verilog

VHDL

Python

Linux

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Job description

Ciena invites students to join the ASIC IP team for a 4-month co-op starting January 2027 in New York. You will design and verify digital blocks for key WaveLogic chipsets and participate in FPGA-based validation.

The role offers exposure to automation, prototype development, and collaboration across engineering teams. Ideal candidates are actively enrolled in EE/CE, have ASIC/FPGA experience, and are proficient in SystemVerilog, Verilog, VHDL, and Python.