ASIC & FPGA Design Co-op - 4-Month IP & Verification

Ciena; New York (NY); On-site; USD 37,000 - 51,000; Part time

Benefits offered by this job

Employee Assistance Program

Company-paid holidays

Paid sick leave

Vacation pay

Job summary

Ciena is offering a 4-month work term starting January 2027 in New York, focusing on ASIC IP design and verification. You will work on digital blocks, cores, and subsystems for ASIC products and FPGA validation, using SystemVerilog, Verilog, VHDL, and Python.

You will collaborate with engineers, develop prototype automation, and apply IEEE/ITU/OIF standards. Strong written and verbal skills are required, with independence and teamwork emphasized.

Qualifications

• Actively enrolled in a Bachelor's degree program in Electrical Engineering or Computer Engineering.
• Experience with ASIC or FPGA development and SystemVerilog/Verilog/VHDL and Python.
• Strong verbal and technical writing skills.
• Self-motivated with the ability to work independently as well as in a team.

Responsibilities

• Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation.
• Collaborate with design and verification engineers on client subsystem and core development activities.
• Implement digital designs using SystemVerilog, Verilog, and VHDL.
• Verify digital designs using SystemVerilog and UVM methodologies.
• Develop and enhance prototype and development automation solutions.
• Apply communications standards knowledge, including IEEE 802.3, ITU, and OIF specifications, within development activities.
• Contribute to digital ASIC development projects through assigned engineering tasks.

Skills

SystemVerilog

Verilog

VHDL

Python

ASIC/FPGA development

Technical writing

Team collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

Ciena is offering a 4-month work term starting January 2027 in New York, focusing on ASIC IP design and verification. You will work on digital blocks, cores, and subsystems for ASIC products and FPGA validation, using SystemVerilog, Verilog, VHDL, and Python.

You will collaborate with engineers, develop prototype automation, and apply IEEE/ITU/OIF standards. Strong written and verbal skills are required, with independence and teamwork emphasized.