ASIC Engineering Technical Leader – CDC

Jobtailor; California (MO); On-site; USD 130,000 - 180,000; Full time

Job summary

Jobtailor is seeking an experienced ASIC designer to define, design, and verify subsystems for Cisco platforms. You will collaborate with a multi-disciplinary team to meet power, performance, and area goals and support high-volume product releases.

The ideal candidate has deep RTL development expertise and strong CDC/RDC knowledge, with experience signing off constraints and waivers and performing static glitch analysis.

Qualifications

• Bachelor’s degree with 8+ years or Master’s with 6+ years or PhD + 3 years of related experience.
• RTL development experience is required.
• CDC/RDC concepts and design implementation experience.
• Maintaining CDC/RDC flow, constraints and waivers.
• Experience with static glitch hazards and synthesis-optimized gate nets.
• Experience with SDC constraints development (preferred).
• Experience with VCS simulation SVA (preferred).

Responsibilities

• Define, design and verify ASIC subsystems for Cisco platforms.
• Contribute to a multi-disciplined engineering team to meet power, performance, and area goals.
• Design, document, and develop ASIC subsystems for release in high volume and quality.
• Lead the CDC/RDC methodology in silicon one chips.
• Design and implement robust RTL with CDC/RDC considerations.
• Spec comprehensive CDC/RDC check flows and work with CAD team to implement.
• Review and approve CDC/RDC constraints and waivers.
• Perform static glitch analysis.
• Improve design with prevention of static glitch hazard.

Skills

RTL development

CDC/RDC concepts

Constraints & waivers signing-off

Static glitch hazard analysis

SVA / SystemVerilog Assertions (SVA)

Education

Bachelor’s degree with 8+ years or related experience

Master’s degree with 6+ years of related experience

PhD + 3 years of related experience

Tools

VCS simulation

SystemVerilog

Job description

Responsibilities

• Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms
• Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products
• Design, document, and develop ASIC subsystems for release in high volume and quality
• Help define the process, methods, and tools for design and implementation of complex developments
• Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
• Design and implement robust and reusable RTL with CDC/RDC considerations
• Spec comprehensive CDC/RDC check flows and work with CAD team to implement
• Review and approve CDC/RDC constraints and waivers
• Perform static glitch analysis
• Improve design with prevention of static glitch hazard

Requirements

• Bachelor’s with 8+ years or related experience, or master’s with 6 + years of related experience, or PhD + 3 years of related experience
• Prior experience with RTL development skills and experiences
• Prior experience with CDC/RDC concepts and relevant design implementation
• Prior Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
• Prior experience with static glitch hazards and relevant analysis on synthesis optimized gate netlists
• Experience on SDC constraints development (Preferred)
• Experience on VCS simulation SVA (SystemVerilog Assertions) (Preferred)