ASIC Engineer Intern: Design, Verification & Tools (Flex)

NWU

Sunnyvale (CA)

On-site

USD 48,000 - 63,000

Full time

14 days+

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Benefits offered by this job

Comprehensive benefits supporting well
Professional development programs
Inclusive work environment with flex

Job summary

NWU is offering an internship for students in Electrical Engineering, Computer Engineering, or Computer Science. You will focus on one ASIC area—Design, Verification, or Tools & Methodologies—and collaborate with senior engineers to learn processes.

The role emphasizes hands-on work with SystemVerilog, UVM, and scripting in Python or C++. You will participate in team meetings, learn project methodologies, and contribute to improving development flows.

Qualifications

  • Pursuing a bachelor’s or master’s degree in a technical field.
  • Coursework in digital logic, computer architecture, or VLSI design is desirable.
  • Exposure to SystemVerilog, UVM, and basic Python/C++ is expected.

Responsibilities

  • Focus on one ASIC area: Design, Verification, or Tools & Methodologies.
  • Collaborate with senior engineers to troubleshoot issues and propose solutions.
  • Participate in team meetings and learn project methodologies.
  • Engage in learning new technologies and best practices in your focus area.
  • Complete assigned tasks efficiently and incorporate feedback.
  • Support ongoing design/verification/test activities as needed.

Skills

Analytical thinking
Communication skills
Time management
Team collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science
Coursework in Digital Logic Design, Computer Architecture, or VLSI Design

Tools

SystemVerilog
UVM
Python
C++

Job description

NWU is offering an internship for students in Electrical Engineering, Computer Engineering, or Computer Science. You will focus on one ASIC area—Design, Verification, or Tools & Methodologies—and collaborate with senior engineers to learn processes.

The role emphasizes hands-on work with SystemVerilog, UVM, and scripting in Python or C++. You will participate in team meetings, learn project methodologies, and contribute to improving development flows.

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