ASIC Engineer I Intern: Build Real Silicon & Systems

Amazon; Cupertino (CA); On-site; USD 125,000 - 142,000; Full time

Job summary

Amazon is seeking an ASIC Engineer I as part of Annapurna Labs, joining a team that designs and optimizes silicon for cloud-scale services. You will contribute to RTL design, verification, and collaboration across disciplines to bring features from concept to silicon.

The role emphasizes hands-on learning, exposure to Verilog/SystemVerilog, and processes spanning design, verification, and physical implementation, with opportunities to impact real products used by millions.

Qualifications

• Bachelor's or Master's degree program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a final graduation date of May 2027 or earlier
• Coursework or project experience in digital logic design and computer architecture
• Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL)
• Understanding of fundamental digital design concepts: combinational and sequential logic, finite state machines, timing, and clocking

Responsibilities

• Designing and implementing RTL for digital logic blocks using Verilog/SystemVerilog
• Developing and running verification environments to validate design functionality and coverage
• Supporting synthesis, timing analysis, and physical design flows
• Debugging design issues through simulation and analysis
• Collaborating with architecture, verification, and physical design teams to take features from specification to silicon
• Documenting your design decisions and presenting your work to the team

Skills

Digital logic design

Computer architecture

Verilog/SystemVerilog

Scripting

Collaboration

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Cadence

Synopsys

Job description

Amazon is seeking an ASIC Engineer I as part of Annapurna Labs, joining a team that designs and optimizes silicon for cloud-scale services. You will contribute to RTL design, verification, and collaboration across disciplines to bring features from concept to silicon.

The role emphasizes hands-on learning, exposure to Verilog/SystemVerilog, and processes spanning design, verification, and physical implementation, with opportunities to impact real products used by millions.