ASIC Engineer Intern — Design, Verification & Tools

Thinklance LLP; Sunnyvale (CA); On-site; USD 48,000 - 63,000; Part time

Benefits offered by this job

Comprehensive benefits

Job summary

Thinklance LLP in Sunnyvale, CA offers a student internship across ASIC Design, Verification, or Tools & Methodologies. You will collaborate closely with senior engineers to explore architectures, write SystemVerilog, build testbenches, and optimize development flows.

Strong communication and time-management skills are essential. The role welcomes Bachelor’s or Master’s students in Electrical/Computer Engineering, Computer Science, or related fields, with coursework in digital logic, computer

Qualifications

• Pursuing a Bachelor's or Master's degree in Electrical/Computer Engineering or Computer Science.
• Familiarity with SystemVerilog, UVM, and basic Python or C++.
• Understanding of ASIC design flow, verification methodologies, and EDA tools.

Responsibilities

• Contribute to architecture investigations and specifications in your focus area.
• Assist in RTL design with SystemVerilog and support synthesis and reviews.
• Develop testbenches, coverage models, and debugging in verification.
• Automate development processes and improve flows as needed.

Skills

SystemVerilog

UVM

Python

C++

ASIC design flow

Education

Bachelors/Masters in EE/CE/CS

Job description

Thinklance LLP in Sunnyvale, CA offers a student internship across ASIC Design, Verification, or Tools & Methodologies. You will collaborate closely with senior engineers to explore architectures, write SystemVerilog, build testbenches, and optimize development flows.

Strong communication and time-management skills are essential. The role welcomes Bachelor’s or Master’s students in Electrical/Computer Engineering, Computer Science, or related fields, with coursework in digital logic, computer