ASIC Engineer Intern: Build Real Silicon & RTL

Amazon

Seattle (WA)

On-site

USD 116,000 - 134,000

Full time

10 days ago

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Job summary

Amazon is seeking an ASIC Engineer Intern at Annapurna Labs to contribute to RTL design for Graviton, Trainium, and Inferentia. You will work on Verilog/SystemVerilog based blocks, with mentoring and real chip development exposure.

You’ll join a team that spans RTL design, verification, and physical design, gaining hands-on experience across the silicon stack from architecture to silicon validation.

Qualifications

  • Currently enrolled in a Bachelor's or Master's degree program with a final graduation date of December 2027 or later
  • Coursework or project experience in digital logic design and computer architecture
  • Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL)
  • Understanding of fundamental digital design concepts: combinational and sequential logic, timing, and clocking

Responsibilities

  • Design RTL for digital logic blocks using Verilog/SystemVerilog
  • Develop and run verification environments to validate design functionality and coverage
  • Supporting synthesis, timing analysis, and physical design flows
  • Debugging design issues through simulation and analysis
  • Collaborating with architecture, verification, and physical design teams to take features from specification to silicon
  • Documenting your design decisions and presenting your work to the team

Skills

Digital logic
Computer architecture
Verilog/SystemVerilog
Timing concepts

Education

Bachelor's or Master's in EE/CE/CS or related

Tools

Cadence
Synopsys
FPGA
Emulator

Job description

Amazon is seeking an ASIC Engineer Intern at Annapurna Labs to contribute to RTL design for Graviton, Trainium, and Inferentia. You will work on Verilog/SystemVerilog based blocks, with mentoring and real chip development exposure.

You’ll join a team that spans RTL design, verification, and physical design, gaining hands-on experience across the silicon stack from architecture to silicon validation.

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