ASIC Engineer, Design Verification

Meta; Austin (TX); On-site; USD 114,000 - 172,000; Full time

Job summary

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure Silicon organization in Austin, TX. You will own verification closure for modules and subsystems, building IP/SoC verification plans and UVM-based testbenches.

Responsibilities include debugging RTL, applying formal verification and emulation to complement simulations, and collaborating with cross-functional teams to ensure first-pass silicon success for data center applications.

Qualifications

• Bachelor's degree in CS/CE or related field, completed before joining Meta.
• 2+ years hands-on SystemVerilog and UVM or C/C++ hardware verification.
• 2+ years verification at block/IP/sub-system/SoC level using SV UVM/OVM.
• Experience with EDA simulators and scripting languages for verification environments.
• Experience debugging RTL failures in simulation or emulation environments.

Responsibilities

• Define and implement verification plans for blocks, IPs, and SoCs to achieve functional coverage.
• Develop and maintain UVM-based testbenches and sequences aligned to test plans.
• Drive verification closure using functional, code, and assertion coverage metrics.
• Debug RTL functional failures and work with ASIC design teams to resolve issues.
• Apply formal verification and emulation to augment simulations and improve efficiency.
• Collaborate with design, architecture, and post-silicon teams to align verification goals.
• Develop reusable verification components like scoreboards, monitors, and coverage models.
• Create automation scripts to improve regression productivity and flows.
• Participate in design reviews and verification planning to identify risks.

Skills

SystemVerilog

UVM

C/C++

Python scripting

RTL debugging

Emulation

Formal verification

Testbench development

Education

Bachelor's degree in Computer Science/Computer Engineering

Tools

EDA simulators

Scripting tools (Python, TCL, Perl, Shell)

Job description

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on Chip (SoC) solutions for data center applications. In this role, you will work alongside experienced engineers focused on developing advanced ASIC solutions that power Meta's data center infrastructure. You will own verification closure for design modules or sub-systems, spanning test planning, UVM-based testbench development, and coverage closure. In addition to simulation-based verification, you will leverage formal verification and emulation methodologies to achieve bug-free silicon. This role offers meaningful opportunities to collaborate with full-stack software, hardware, ASIC design, emulation, and post-silicon validation teams toward first-pass silicon success.

ASIC Engineer, Design Verification Responsibilities:

• Define and implement block, IP, and SoC-level verification plans to enable comprehensive functional coverage across design hierarchies
• Develop and maintain UVM-based testbenches and functional test sequences aligned to the verification test plan
• Drive verification closure using defined metrics including functional coverage, code coverage, and assertion coverage
• Debug and root-cause functional failures in RTL designs, partnering closely with the ASIC design team to resolve issues
• Apply formal verification and emulation techniques to complement simulation-based approaches and improve verification efficiency
• Collaborate with design, architecture, and post-silicon validation teams to align on verification goals and ensure design quality
• Develop reusable verification infrastructure components including scoreboards, monitors, and coverage models
• Contribute to scripting and automation flows using Python, TCL, or Shell to improve verification productivity and regression management
• Participate in design reviews and verification planning discussions to identify potential design risks early in the development cycle

Minimum Qualifications:

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• 2+ years of hands-on experience in SystemVerilog and UVM-based verification methodology or C/C++ based hardware verification
• 2+ years of experience in block, IP, sub-system, or SoC-level verification using SystemVerilog UVM or OVM methodologies
• Experience with EDA simulation tools and scripting languages such as Python, TCL, Perl, or Shell for building verification environments and flows
• Experience debugging RTL functional failures and performing root-cause analysis in a simulation or emulation environment

Preferred Qualifications:

• Experience with Emulation platform usage for Pre-Si verification
• Experience verifying ARM or RISC-V based sub-systems or SoCs, or data center application designs such as AI/ML accelerators, networking, or video processing ASICs
• Experience with IP or integration verification of high-speed interfaces such as PCIe, DDR, or Ethernet
• Experience developing UVM-based verification environments from scratch, including environment architecture, sequencers, and coverage models
• Experience with Chip Debug Logic, Telemetry and/or RAS

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affremative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$114,000/year to $172,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.