ASIC Engineer

Janestreet; New York (NY); On-site; USD 100,000 - 150,000; Full time

Job summary

Janestreet is seeking an experienced ASIC Engineer to join their Ultra Low Latency team in New York. This role involves designing, testing, and deploying advanced hardware designs while collaborating with various teams across the firm.

The ideal candidate will have over 4 years of practical experience in RTL design and ASIC design, along with a passion for leveraging software engineering techniques to enhance hardware development. Janestreet promotes innovative tools to improve efficiency and reliability in hardware engineering.

Qualifications

• 4+ years practical experience in RTL design and verification.
• Experience in ASIC design using Synopsys or Cadence.
• Familiarity with software engineering techniques.

Responsibilities

• Design, test, and deploy advanced hardware designs.
• Collaborate with teams across trading, networking, and research infrastructure.
• Work on FPGA-based and ASIC-based technologies.

Skills

RTL design and verification

ASIC design (Synopsys or Cadence)

Programming in Python, C++, Java, or Haskell

Job description

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)