Senior ASIC Engineer - Low-Latency Hardware & Tools

Janestreet; New York (NY); On-site; USD 100,000 - 150,000; Full time

Job summary

Janestreet is seeking an experienced ASIC Engineer to join their Ultra Low Latency team in New York. This role involves designing, testing, and deploying advanced hardware designs while collaborating with various teams across the firm.

The ideal candidate will have over 4 years of practical experience in RTL design and ASIC design, along with a passion for leveraging software engineering techniques to enhance hardware development. Janestreet promotes innovative tools to improve efficiency and reliability in hardware engineering.

Qualifications

• 4+ years practical experience in RTL design and verification.
• Experience in ASIC design using Synopsys or Cadence.
• Familiarity with software engineering techniques.

Responsibilities

• Design, test, and deploy advanced hardware designs.
• Collaborate with teams across trading, networking, and research infrastructure.
• Work on FPGA-based and ASIC-based technologies.

Skills

RTL design and verification

ASIC design (Synopsys or Cadence)

Programming in Python, C++, Java, or Haskell

Job description

Janestreet is seeking an experienced ASIC Engineer to join their Ultra Low Latency team in New York. This role involves designing, testing, and deploying advanced hardware designs while collaborating with various teams across the firm.

The ideal candidate will have over 4 years of practical experience in RTL design and ASIC design, along with a passion for leveraging software engineering techniques to enhance hardware development. Janestreet promotes innovative tools to improve efficiency and reliability in hardware engineering.