ASIC DMA Design Engineer - Neural Engine

Apple Inc.; Sunnyvale (CA); On-site; USD 129,300 - 194,700; Full time

Benefits offered by this job

Stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Sunnyvale, CA seeks an ASIC Design Engineer to contribute to ANE DMA design, moving data between memory and compute for the Apple Neural Engine. You will collaborate across front‑end cycles with architecture and verification teams to meet performance, power, and area targets.

Responsibilities include RTL development, synthesis, timing closure, and rigorous verification, ensuring correct behavior and design intent through all phases.

Qualifications

• Bachelors Degree plus 0 years of industry experience.

Responsibilities

• Write well-parameterized RTL for synthesis, timing, area and power with assertions and cover points.
• Perform front-end implementation tasks: synthesis, timing closure, area and power analysis, linting, and equivalence checks.
• Collaborate with design and architecture teams to meet performance, power, and area targets.
• Work with verification teams to ensure functional correctness and full test coverage.

Skills

Verilog/SystemVerilog

Digital design fundamentals

AMBA bus protocols

System-level concepts (SoC data flow)

Scripting languages (Python/Perl/Tcl)

Technical writing

Education

Bachelor's degree

Job description

Apple Inc. in Sunnyvale, CA seeks an ASIC Design Engineer to contribute to ANE DMA design, moving data between memory and compute for the Apple Neural Engine. You will collaborate across front‑end cycles with architecture and verification teams to meet performance, power, and area targets.

Responsibilities include RTL development, synthesis, timing closure, and rigorous verification, ensuring correct behavior and design intent through all phases.