ASIC Design Verification Engineer, TPU Compute

Google; Sunnyvale (CA); On-site; USD 138,000 - 198,000; Full time

Job summary

Google is seeking an ASIC Design Verification Engineer to shape the future of AI/ML hardware acceleration. You will drive cutting-edge TPU technology powering Google's demanding AI/ML applications and verify complex digital designs with a focus on TPU architecture integrated into AI/ML-driven systems.

You will join a team developing cutting-edge ASICs used to accelerate computation in data centers, contributing to architecture, documentation, and verification for next-generation data center

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CS.
• 4 years of experience with design verification.
• Experience verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
• Master's degree or PhD in EE/CE/CS with focus on computer architecture.
• 6 years of experience with industry standard tools, languages and methodologies for silicon-based ICs.
• Experience with 3+ SoC projects.
• Strong problem-solving and teamwork skills.

Responsibilities

• Plan verification of complex digital design blocks by understanding specs and coordinating with design engineers to identify key verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to show progress toward tape-out.

Skills

Design verification

SystemVerilog

UVM

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with emphasis on computer architecture

Job description

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon‑based ICs and chips.
• Experience with three or more SoC projects/cycles.
• Experience verifying compute IPs.
• Strong problem‑solving, analytical, and communication skills with the ability to work effectively in a team environment.

About the Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an ASIC Design Verification Engineer, you will be part of a team developing cutting‑edge ASICs used to accelerate computation in data centers. You will have dynamic, multi‑faceted responsibilities in areas such as project definition, design verification and silicon bring‑up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits

Responsibilities

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create a constrained‑random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner‑cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress toward tape‑out.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.