ASIC Design Verification Engineer, Google Cloud

Google; Sunnyvale (CA); On-site; USD 117,000 - 166,000; Full time

Job summary

Google in Sunnyvale is seeking an ASIC Design Verification Engineer to shape the future of AI/ML hardware acceleration. You will work on innovative TPU technology that powers Google’s AI applications and help develop solutions to accelerate computation in data centers.

The ideal candidate will have a Bachelor's degree in Electrical Engineering or a related field, along with experience in design verification and SystemVerilog. The base salary range for this full-time position is $117,000-$166,000, plus bonus and equity.

Qualifications

• 1 year of experience in design verification.
• Familiarity with coverage analysis tools.
• Excellent problem-solving and debugging skills.

Responsibilities

• Plan the verification of complex digital design blocks.
• Create a constrained-random verification environment using SystemVerilog.
• Identify and write coverage measures for verification.

Skills

Design verification expertise

SystemVerilog

Problem-solving skills

Debugging skills

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in Electrical Engineering

Tools

Universal Verification Methodology (UVM)

Verdi

Questa

Job description

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 1 year of experience in design verification.
• Experience with SystemVerilog/Verilog.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Universal Verification Methodology (UVM) testbenches and methodologies.
• Experience developing and executing test plans.
• Familiarity with coverage analysis tools (e.g., Verdi, Questa).
• Proficiency in SystemVerilog, including object-oriented programming, SystemVerilog Assertions (SVAs) and functional coverage.
• Excellent problem-solving and debugging skills.

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an Application‑Specific Integrated Circuit (ASIC) Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi‑faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full‑time position is $117,000-$166,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
• Create a constrained‑random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner‑cases.
• Debug tests with design engineers to deliver correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape‑out.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .