ASIC Design Engineer (Video Silicon IP)- Multimedia Lab

ByteDance; San Jose (CA); On-site; USD 162,000 - 317,000; Full time

Job summary

ByteDance is seeking an ASIC Design Engineer for its Video Silicon IP team in the U.S. The role focuses on designing high-performance video codec hardware (ASIC/FPGA) and RTL for multi-standard codecs, with collaboration across architecture, algorithm, and verification groups.

You will implement RTL for codec pipelines, support verification, and ensure timing closure while optimizing area and power. A strong background in SystemVerilog and VLSI concepts is required.

Qualifications

• MS/PhD in Electrical Engineering or related field.
• 2 years of ASIC front-end design as primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM, DPI, and C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, AXI/APB, SV assertion basics.
• Python scripting for EDA flow automation.

Responsibilities

• Design high-performance, low-power video processing IPs within the Video Silicon IP team.
• Develop RTL for video codec pipeline stages including intra/inter prediction, transform/quantization, entropy coding.
• Collaborate with architecture, algorithm and verification teams to translate specifications into hardware.
• Drive functional correctness with verification using directed/constrained-random UVM test benches; debug RTL coverage.
• Understand synthesis, timing analysis, and CDC/RDC checks; assist floor planning and timing closure.

Skills

SystemVerilog RTL

Verilog/SystemVerilog

UVM

Python scripting

C++ (DPI)

Education

MS/PhD in Electrical Engineering or related field

Tools

UVM/DPI/C++

Job description

Responsibilities

Team Introduction

The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
• Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec standard specifications and proprietary codec improvements into implementable hardware architectures.
• Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
• Drive functional correctness in partnership with the verification team using directed and constrained-random UVM test benches; debug and close RTL coverage metrics.
• Understand synthesis, timing analysis, and CDC/RDC checks; work with physical design on floor plan and timing closure guidance.

Qualifications

Minimum Qualifications

• M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 2 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
• Scripting proficiency in Python for EDA flow automation.

Preferred Qualifications

• Experience with Video Codec (H.265/HEVC, H.266/VVC, AV1, VP9, or H.264/AVC) is a big plus.
• Experience with relevant ISP or machine learning based image/video compression.
• Experience with FPGA prototyping for pre-silicon codec validation.
• Practical experience using LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL design workflows.

About Us

Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create content.

Why Join ByteDance

Inspiring creativity is at the core of ByteDance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day. As ByteDancers, we strive to do great things with great people. We lead with curiosity, humility, and a desire to make impact in a rapidly growing tech company. By constantly iterating and fostering an "Always Day 1" mindset, we achieve meaningful breakthroughs for ourselves, our Company, and our users. When we create and grow together, the possibilities are limitless. Join us.

Diversity & Inclusion

ByteDance is committed to creating an inclusive space where employees are valued for their skills, experiences, and unique perspectives. Our platform connects people from across the globe and so does our workplace. At ByteDance, our mission is to inspire creativity and enrich life. To achieve that goal, we are committed to celebrating our diverse voices and to creating an environment that reflects the many communities we reach. We are passionate about this and hope you are too.

Reasonable Accommodation

ByteDance is committed to providing reasonable accommodations in our recruitment processes for candidates with disabilities, pregnancy, sincerely held religious beliefs or other reasons protected by applicable laws. If you need assistance or a reasonable accommodation, please reach out to us at https://tinyurl.com/RA-request

Job Information

【For Pay Transparency】Compensation Description (Annually) The base salary range for this position in the selected city is $162000 - $316800 annually. Compensation may vary outside of this range depending on a number of factors, including a candidate’s qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.

Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure). The Company reserves the right to modify or change these benefits programs at any time, with or without notice.

For Los Angeles County (unincorporated) Candidates: Qualified applicants with arrest or conviction records will be considered for employment in accordance with all federal, state, and local laws including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Our company believes that criminal history may have a direct, adverse and negative relationship on the following job duties, potentially resulting in the withdrawal of the conditional offer of employment: 1. Interacting and occasionally having unsupervised contact with internal/external clients and/or colleagues; 2. Appropriately handling and managing confidential information including proprietary and trade secret information and access to information technology systems; and 3. Exercising sound judgment.