ASIC Design Engineer — RTL/SoC for GPUs (Equity)

NVIDIA; United States; On-site; USD 120,000 - 210,000; Full time

Job summary

NVIDIA is seeking an ASIC Design Engineer in the United States to design high-performance RTL blocks, craft micro-architectures, and collaborate across teams to validate silicon at the RTL level.

The role requires a BS/MS in EE/CE/CS with 2+ years of RTL experience, Verilog proficiency, and strong scripting in Perl/Python. Base salary is tiered by level, with equity and benefits. Applications accepted until the posting date.

Qualifications

• BS/MS Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
• 2+ years of relevant RTL design work experience.
• Strong in micro-architecture and RTL development (Verilog), as well as entire front-end flows including logic synthesis, power, and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Excellent interpersonal skills and a proven ability to work well in a team.

Responsibilities

• Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications.
• Analyzing architectural trade-offs based on features, performance requirements, and area/power constraints.
• Crafting micro-architecture, implementing them in RTL, and delivering fully verified, synthesis/timing clean builds.
• Collaborating closely with architects, other designers, and pre and post silicon verification teams to deliver world-class RTL builds.
• Working on a diverse list of IPs, including GPU's time distribution system, engine scheduler, interrupt controllers, and copy engines.
• Assisting the silicon bring-up team in debugging and post-silicon validation activities.]
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• JOB SUMMARY

Skills

C/C++

Perl

Python

Education

BS/MS Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Verilog

Job description

NVIDIA is seeking an ASIC Design Engineer in the United States to design high-performance RTL blocks, craft micro-architectures, and collaborate across teams to validate silicon at the RTL level.

The role requires a BS/MS in EE/CE/CS with 2+ years of RTL experience, Verilog proficiency, and strong scripting in Perl/Python. Base salary is tiered by level, with equity and benefits. Applications accepted until the posting date.