ASIC Design Engineer — Hybrid, Equity & Impact

NVIDIA Gruppe; Austin (TX); Hybrid; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Design Engineer to join our team in Austin. You will develop and deploy in-house tools, own verification blocks, and act as a DevOps engineer for automated RTL generation. The role emphasizes collaboration across multi-disciplinary teams and hands-on Verilog design.

Base salaries vary by level: roughly 116k–189.75k (Level 2) or 136k–218.5k (Level 3), with eligibility for equity and benefits. The posting indicates hybrid work in a dynamic, inclusive environment.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of proven experience preferred.
• Solid understanding of fundamental digital design concepts with hands‑on experience in Verilog.
• Proficiency in scripting using modern Python and/or Perl.
• Experience with Unix/Linux shell scripting and Makefiles.
• Strong ability to collaborate with multi‑functional teams and effectively communicate technical details.

Responsibilities

• Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.
• Take ownership of tools that verify common design blocks used in all products at NVIDIA.
• Act as a DevOps engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
• Build new workflows and methodologies to ensure smooth integration into various IP development environments.

Skills

Team collaboration

Communication

Education

Bachelor’s/Master’s degree in Electrical or Computer Engineering

Tools

Verilog

Python

Perl

Unix/Linux shell scripting

Makefiles

Job description

NVIDIA is seeking an ASIC Design Engineer to join our team in Austin. You will develop and deploy in-house tools, own verification blocks, and act as a DevOps engineer for automated RTL generation. The role emphasizes collaboration across multi-disciplinary teams and hands-on Verilog design.

Base salaries vary by level: roughly 116k–189.75k (Level 2) or 136k–218.5k (Level 3), with eligibility for equity and benefits. The posting indicates hybrid work in a dynamic, inclusive environment.