ASIC Design Engineer Intern

Ambarella; United States; On-site; USD 120,000 - 160,000; Full time

Job summary

A Ambarella is seeking a highly capable engineer to design and verify video processing and AI accelerator cores for edge applications. You will work on video compression, image processing and neural network logic, implementing these in Verilog and SystemVerilog, while developing test benches and coverage with UVM and C++.

You will contribute to RTL synthesis, timing closure, and chip bring-up in a collaborative environment.

Qualifications

• Master’s degree in Electrical/Electronics/Computer Engineering with 0–5 years of experience.
• Strong understanding of computer architecture, logic design and VLSI design.
• Knowledge of SystemVerilog, Verilog, and Perl.
• Knowledge of design verification and functional coverage.
• Ability to program scripting languages and write assembly language programs.
• Strong communication skills and good team player.
• Knowledge of logic synthesis and timing closure.

Responsibilities

• Design and implement video compression logic, image processing logic, neural network and AI accelerator logics, and processor cores in Verilog and SystemVerilog.
• Synthesize RTL and optimize for timing, area and power.
• Develop unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using SystemVerilog, UVM, C++, and Perl scripts.
• Develop test plans, random and directed test cases, performing logic verification, and functional coverage analysis.
• Develop front-end methodologies and tool flows.
• Participate in chip bring-up and testing.

Skills

Verilog

SystemVerilog

UVM

C++

Perl

VLSI design

Computer architecture

Education

Master’s degree in Electrical/Electronics/Computer Engineering

Tools

BFMs

Job description

AI Vision Processors For Edge ApplicationsOur solutions make cameras smarter by extracting valuable data from high-resolution video streams.Job DescriptionJob DescriptionPosition Responsibilities:Designing and implementing video compression logic, image processing logic, neural network and AI accelerator logics, and processor cores, in Verilog and System Verilog.Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.Synthesize and optimize RTL for timing, area and power.Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts.Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis.Developing front-end methodologies and tool flows.Participating in chip bring-up and testing.Requirements :Master’s degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.Good understanding of computer architecture, logic design and VLSI design.Knowledge of System Verilog, Verilog, and Perl.Knowledge of design verification, and functional coverage.Ability to program scripting languages and the ability to write assembly language programs.Strong communication skills and a good team player.Knowledge of logic synthesis and timing closer