Verification Engineer Intern

ambarella; United States; On-site; USD 34,000 - 48,000; Full time

Job summary

Ambarella is offering exciting internship opportunities for students nearing the completion of their master's degree, focusing on VLSI design, programming and computer architecture. Interns will work on SoCs with DSP and computer vision blocks, CPUs and co-processors.

The role includes developing test benches, generating tests, building coverage monitors and creating tooling to drive simulations and performance analyses. Strong Verilog/SystemVerilog and C/C++ skills are expected.

Qualifications

• Pursuing a master's degree in a related field.
• Experience with Verilog/SystemVerilog and UVM.
• Familiarity with C/C++ and scripting languages (Python/Perl).

Responsibilities

• Develop test benches (or parts thereof), write and debug tests and RTL logic.
• Write Random Test Generators to automatically and intelligently generate the tests.
• Write coverage monitors, checkers, assertions and collect statistics.
• Create tools, scripts and utilities to aid in creating stimulus and analyzing the results of simulations, including performance measurements.

Skills

Verilog

SystemVerilog

UVM

C

C++

Perl

Python

Assembly

Education

Master's degree in progress

Job description

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Ambarella has some exciting internship opportunities for self-motivated and creative students near completion of their master's degree. We are looking for talented engineers who possess a strong interest in VLSI design, programming and computer architecture.

Ambarella designs complex SoCs which include custom DSP and computer vision blocks, CPUs and co-processors.

Some example responsibilities will include:

• Develop test benches (or parts thereof), write and debug tests and RTL logic.
• Write Random Test Generators to automatically and intelligently generate the tests.
• Write coverage monitors, checkers, assertions and collect statistics.
• Create tools, scripts and utilities to aid in creating stimulus and analyzing the results of simulations, including performance measurements.

The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be able to pick up missing skills quickly, deliver their assignments on time, and present their work at the end of the program.