ASIC Design Engineer II - Vision Processors

Ambarella; Northern (KY); Hybrid; USD 130,000 - 160,000; Full time

Job summary

Ambarella seeks an ASIC Design Engineer II to design video processing cores and accelerators using Verilog and SystemVerilog. You will contribute to RTL, timing closure, and verification, collaborating with a multidisciplinary team to bring high-performance edge solutions to market.

This role offers growth opportunities in autonomous cameras and smart devices, with a base pay range of $130,000 to $160,000 and comprehensive benefits. On-site collaboration at the US HQ is expected.

Qualifications

• Master's degree in Electrical, Electronics, or Computer Engineering.
• 0–5 years of relevant experience.
• Strong understanding of computer architecture and VLSI design principles.
• Proficiency in Verilog/SystemVerilog and Perl.

Responsibilities

• Design and implement video processing cores, accelerators, and memory subsystems using Verilog and SystemVerilog.
• Perform logic design, implementation, and verification.
• Synthesize and optimize RTL for performance, area, and power.
• Collaborate with verification team to address coverage gaps.

Skills

Verilog

SystemVerilog

Perl

VLSI design

Education

Master's degree in Electrical/Electronics/Computer Engineering

Tools

RTL Synthesis Tools

Job description

Ambarella seeks an ASIC Design Engineer II to design video processing cores and accelerators using Verilog and SystemVerilog. You will contribute to RTL, timing closure, and verification, collaborating with a multidisciplinary team to bring high-performance edge solutions to market.

This role offers growth opportunities in autonomous cameras and smart devices, with a base pay range of $130,000 to $160,000 and comprehensive benefits. On-site collaboration at the US HQ is expected.