ASIC Design Engineer

OVT group; Santa Clara (CA); On-site; USD 120,000 - 145,000; Full time

Job summary

A leading technology company is seeking an ASIC Design Engineer in Santa Clara, California. The role includes responsibilities such as designing micro-architecture, participating in RTL coding, and validating designs through FPGA emulation. Candidates should have a degree in Electrical or Computer Engineering and at least 2 years of relevant ASIC design experience.

Qualifications

• 2+ years of ASIC design experience required.
• Hands-on experience in ASIC chip design and integration essential.
• Knowledge of chip-level tape out procedure crucial.

Responsibilities

• Design and implement module level micro-architecture.
• Participate in both top level and module level RTL coding and integration.
• Generate test cases for the module level and chip level.

Skills

Verilog

System Verilog

C

C++

Digital Image Processing

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

UVM

DFT

Job description

Responsibilities:

• Design and implement module level micro-architecture
• Participate in top-level implementation and integration
• Participate in both top level and module level RTL coding, simulation, synthesis and timing closure
• Generate test cases for the module level and chip level.
• Participate in FPGA emulation and post-silicon validation.
• Write design specification

Requirements:

• BS in Electrical or Computer Engineering or related field or related experience, or MS in Electrical or Computer Engineering plus related experience
• 2+ years of ASIC design experience with knowledge of ASIC design flow, including hands-on experience in ASIC chip design and integration.
• Requires knowledge of Verilog, system Verilog, C or C++ languages, digital image processing and chip-level tape out procedure from initial PRD, design, verification, timing closure, FPGA emulation and ECO.
• Knowledge of display technology is a plus
• Knowledge of UVM is a plus
• Knowledge of DFT(Scan/MBIST/Functional Pattern) is a plus

Annual base salary for this role in California, US is expected to be between $120,000 - $145,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.