ASIC Design Engineer

Chipright; United States; Remote; USD 120,000 - 160,000; Full time

Job summary

A leading technology company is seeking a Senior ASIC Digital Design Engineer. The ideal candidate will have over 8 years of experience in RTL design and be proficient in SystemVerilog and scripting languages. This is an exciting opportunity to contribute to innovative projects in a dynamic environment.

Qualifications

• Minimum of 8 years of related experience.
• Proficient in scripting languages like Python, Tcl, Perl, Unix shell.
• Familiar with RTL best practices and verification flows.

Responsibilities

• Perform RTL design with SystemVerilog.
• Conduct linting checks and static timing analysis.
• Participate in synthesis and verification processes.

Skills

RTL Design

SystemVerilog

Scripting languages

Communication

Education

BS/MS degree

Job description

Senior Digital Design Engineer

We’re looking for a Senior ASIC Digital Design Engineer with the following qualifications and experience:

Experience required

1. RTL Design with SystemVerilog
2. Linting checks with SpyGlass
3. STA (Static Timing Analysis)
4. Synthesis
5. Experience with formal verification (a plus)

Key Qualifications

1. BS/MS degree with a minimum of 8 years of related experience
2. Proficient in scripting languages (Python, Tcl, Perl, Unix shell)
3. Familiar with RTL best design practices with SystemVerilog
4. Familiar with implementation and verification front-end flows
5. Strong communication skills